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  1. SAFe Program
  2. SP-1772

TDC MVP0 Build 2 - TALON Async Updates

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    • Feature
    • Must have
    • PI11
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    • Obs Mgt & Controls
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      Prior to integration of the correlator, TDC MVP0 Build1 requires a number of firmware updates to bring existing development inline with the TALON Asynchronous design.  This work is required before expanding TDC to use multiple receptors and will be easiest to do sooner (before integrating the correlator) rather than later.

       

      Show
      Prior to integration of the correlator, TDC MVP0 Build1 requires a number of firmware updates to bring existing development inline with the TALON Asynchronous design.  This work is required before expanding TDC to use multiple receptors and will be easiest to do sooner (before integrating the correlator) rather than later.  
    • Hide

      1) Per-sample timestamping is implemented after the VCC channelizer.

      2) Per-sample timestamping is implemented after the 16K imaging channelizer.

      3) Corner turn IP updated to handle long term receptor drop-outs.

      4) Test benches updated with test cases for receptor drop-outs and new timestamp scheme.

      5) Hardware tests executed with expected results.

      Show
      1) Per-sample timestamping is implemented after the VCC channelizer. 2) Per-sample timestamping is implemented after the 16K imaging channelizer. 3) Corner turn IP updated to handle long term receptor drop-outs. 4) Test benches updated with test cases for receptor drop-outs and new timestamp scheme. 5) Hardware tests executed with expected results.
    • 5
    • 4
    • Team_CIPA
    • Sprint 5
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      Timestamping capability was added to the very coarse channelizer (VCC) which was developed in PI8 (SP-1149), as well as the 16k channelizer which was integrated in PI9 (SP-1379). These designs take a very long time to simulate, so we added simple behavioral models of these designs which simulate quickly and enabled faster testing of the new timestamping logic.

      The corner turner (developed in PI10 - SP-452) was updated to handle changes associated with the new Async TALON architecture, in particular handling of receptor dropouts, and the ability for receptors to (re)join the processing pipeline without losing timing alignment.

      Due to integration challenges, testing on hardware was not fully achieved. However, this work has significantly progressed the CIPA team's pivot to the Async TALON architecture. All other aspects of the feature were achieved.

      Show
      Timestamping capability was added to the very coarse channelizer (VCC) which was developed in PI8 ( SP-1149 ), as well as the 16k channelizer which was integrated in PI9 ( SP-1379 ). These designs take a very long time to simulate, so we added simple behavioral models of these designs which simulate quickly and enabled faster testing of the new timestamping logic. The corner turner (developed in PI10 - SP-452 ) was updated to handle changes associated with the new Async TALON architecture, in particular handling of receptor dropouts, and the ability for receptors to (re)join the processing pipeline without losing timing alignment. Due to integration challenges, testing on hardware was not fully achieved. However, this work has significantly progressed the CIPA team's pivot to the Async TALON architecture. All other aspects of the feature were achieved.
    • 13.2
    • Stories Completed, Integrated, Outcomes Reviewed, Satisfies Acceptance Criteria, Accepted by FO

    Description

      Firmware IP blocks developed prior to the adoption of TALON Asynchronous design are largely untouched by the change.

      However, integration of the IP blocks needs to be done in a manner to support two key concepts of TALON Asynchronous design:

      1. Processing rate is tied to input data rate and when input data stops, processing must stop as well until input data resumes.
      2. Timestamp of each sample is known and used extensively for data management.

      The TDC MVP0 Build 1 bitstream must be updated to support these concepts prior to further extending the signal chain.  Tasks for this feature include:

      1. Implement per-sample timestamping scheme in a cohesive manner from the output of the VCC channelizer through to the output of the fine channel corner turn.
      2. Update corner turn IP to handle long term receptor drop-outs
      3. Update test benches for test cases for receptor drop outs and timestamping
      4. Test in hardware

       

       

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          Feature - A Feature is a service that fulfills a stakeholder need. Each feature includes a benefit hypothesis and acceptance criteria, and is sized or split as necessary to be delivered by a single Agile Release Train (ART) in a Program Increment (PI). SP-1609 TDC MVP0 Build 2 - Preparation for Correlator Integration

          • Could have - Items labelled as "Could have" are desirable but not necessary and could improve the user experience or customer satisfaction for a little development cost. These will typically be included if time and resources permit.
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                b.alachkar Alachkar, Bassem
                S.Harrison Harrison,Stephen
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                Feature Progress

                  Story Point Burn-up: (100.00%)

                  Feature Estimate: 5.0

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