Uploaded image for project: 'SAFe Program'
  1. SAFe Program
  2. SP-1609

TDC MVP0 Build 2 - Preparation for Correlator Integration

Change Owns to Parent OfsSet start and due date...
    XporterXMLWordPrintable

Details

    • Feature
    • Could have
    • PI11
    • None
    • Obs Mgt & Controls
    • Hide

      Progressing the fine channel transport infrastructure towards end-to-end processing will reduce the risk of integrating the TDC correlator IP. 

       

      Show
      Progressing the fine channel transport infrastructure towards end-to-end processing will reduce the risk of integrating the TDC correlator IP.   
    • Hide

      Fine channel transport physical layer (SLIM) is tested in simulation and ready for integration.

      Fine channel packetization is tested in simulation and ready for integration.

      Show
      Fine channel transport physical layer (SLIM) is tested in simulation and ready for integration. Fine channel packetization is tested in simulation and ready for integration.
    • 6
    • 6
    • Team_CIPA
    • Sprint 5
    • Hide

      The TDC MVP was progressed by developing the fine channel packetizer which follows the Corner Turn IP that was integrated in PI10 (SP-452) and updated for the Async TALON architecture in PI11 (SP-1772). The fine channel packetizer splits the data output from the corner turn into multiple streams that are suitable for distribution to the FSPs over the Serial Lightweight Interconnect Mesh (SLIM) links. The SLIM IP was also updated in preparation for integration. The CIPA team is now well-positioned to integrate the correlator and sync buffer in PI12 (SP-1792).

      Show
      The TDC MVP was progressed by developing the fine channel packetizer which follows the Corner Turn IP that was integrated in PI10 ( SP-452 ) and updated for the Async TALON architecture in PI11 ( SP-1772 ). The fine channel packetizer splits the data output from the corner turn into multiple streams that are suitable for distribution to the FSPs over the Serial Lightweight Interconnect Mesh (SLIM) links. The SLIM IP was also updated in preparation for integration. The CIPA team is now well-positioned to integrate the correlator and sync buffer in PI12 ( SP-1792 ).
    • 12.1
    • Stories Completed, Integrated, Outcomes Reviewed, NFRS met, Satisfies Acceptance Criteria, Accepted by FO

    Description

      Advance the fine channel transport infrastructure to prepare the FPGA design for integrating an 8 receptor / 100 MHz parameterization of the TDC correlator in the next PI.

       

       

       

       

       

      Attachments

        Issue Links

          Structure

            Activity

              People

                b.lewis Lewis, Ben
                S.Harrison Harrison,Stephen
                Votes:
                0 Vote for this issue
                Watchers:
                2 Start watching this issue

                Feature Progress

                  Story Point Burn-up: (100.00%)

                  Feature Estimate: 6.0

                  IssuesStory Points
                  To Do00.0
                  In Progress   00.0
                  Complete941.0
                  Total941.0

                  Dates

                    Created:
                    Updated:
                    Resolved:

                    Structure Helper Panel