TDC VCC Build 1

 VCC Build 1 high-level design,

Firmware bitstream that consists of: 

• VCC Build 0
• Defined interfaces between DSP blocks.
• Very Coarse Channelizer for TDC – implement and simulate - TG
• 64-bit RDMA - WK
• Frequency slice circuit switch - JL
• Packet to Stream shim - JL 

Plus software to control the above and analyze the results for the purpose of demonstration. 

The 20-channel very coarse channelizer (VCC) digital signal processing block was designed for the Stratix10 FPGA and tested in functional simulation. This met the expected resource utilization and performance targets.

A common streaming interface bus format was developed for use between DSP blocks, based on the VHDL fixed-point libraries (internally: dsp_lib). This is used for both polyphase and single-phase interfaces. The packet to stream shim converts between DSH packet format and this format. The VCC uses this format for both ingress and egress interfaces. The 16k channelizer (SP-1276) also uses this format.

This feature successfully built upon VCC Build 0 while also developing the infrastructure required to test the VCC on the Talon DX hardware. This infrastructure will be reused in future VCC builds.

This is the first time establishing a remote direct memory access (RDMA) link between the Talon-DX and a PC. This method of worked very well for transferring large volumes of data from the Talon board. An analysis tool was developed to process this data and check that the VCC operates as expected at full speed on the Talon-DX, confirming the earlier functional simulation result.

The demo showed all of the new feature in action, controlling the circuit switch to capture the frequency slices output from the VCC, transferred to the Dell server using RDMA over 100GbE, and processed to produce the stitched-together spectrum from all frequency slices. Waterfall plots and histograms were also shown for a single frequency slice.