MID.CBF to SDP interface - Prototype minimally functional visibility data path

Develop a minimally functional firmware datapath from the visibility output of the Long Term Accumulator (LTA mostly existing code for Mid) to a 10/25Gbps ethernet interface.

Requires code to do normalization and conversion from fixed-point to floating point.

Code to pack visibilities into SPEAD heaps.

Code to split heaps into UDP packets.

Code to wrap UDP into IP and Ethernet.

Physical tests will be performed on an Arria10 SoC development kit if a TalonDX board is unavailable.

Each Mid.FSP FPGA will generate up to 102.5 million visibilities per second. Each visibility is 35 bytes = 280bits. So the peak output data rate is 102.5M*208=28.7Gbps plus overhead.

4.5% overhead brings it to 30Gbps.

Output interfaces are 25Gbps each, so a multi-ported implementation needs to be developed.