Verification of the Harmonic Summing module in the Intel Agilex FDAS FPGA

In PI18 feature SP-3108 the three DDR SDRAM version of the Intel Agilex Fourier Domain Acceleration Search (FDAS) FPGA was created (two DDR SDRAMs used to store the Filter Output Plane and one to store the incoming observation data). This version of FDAS met the required processing time and it was also possible to confirm that the Convolution (CONV) module had correctly created the Filter Output Plane (FOP).

However the Harmonic Summing (HSUM) module remains unproven since the updates from Intel Arria 10 to Agilex family and the increase in the number of DDR SDRAMs used to store the FOP which is interrogated by the HSUM module.

Hence it necessary to validate the HSUM module to confirm the Intel Agilex FDAS FPGA with three DDR interfaces is operating correctly and identifies pulsar candidates as expected.

In addition, after PI18 closure, further testing  has identified that occasionally the HSUM module fails to report that it has completed its task. Over-night repetative tests with a “full HSUM configuration” (262,144 pulsar fundamental frequencies, 21 fundamental orbital accelerations and 11 acceleration ambiguity slopes) as would be used in the SKA telescope (run every 250ms) have not reported any problems. However with some “short HSUM configurations” (30 pulsar fundamental frequencies, 1 fundamental orbital acceleration and 1 acceleration ambiguity slope) which are only testing a small pulsar frequency/orbital acceleration range, HSUM occasionally does not appear to have completed the task (sometimes OK for 10,000 runs and then fails to complete approxmately 10 times in 100 runs). This needs to be investigated to identify and if necessary fix the problem as it indicates a lack of robustness.

• The Harmonic Summing (HSUM) module shall be tested to confirm it successfully identifies an easily identifable the pulsar signature within a Filter Output Plane (FOP) created using MATLAB. This easily identifable pulsar signature in the FOP shall be used to confirm that the HSUM module is correctly identifying and summing the power levels of the harmonics and reporting threshold crossings.
• The appropriate MATLAB script in AT4-716 shall be used to perform a Fourier transform of the .tim file (mimicking the CXFT function) to create a spectrum that can be used as the observation input to the FDAS FPGA. This mimicks the real world situation where the pulsar signature is embedded in a background of noise. The Intel Agilex FDAS FPGA shall be used to process the observation and output will be compared to and checked for the expected pulsar candidate as predicted by the MATLAB models in AT4-716.
• The Harmonic Summing (HSUM) module shall be tested to ensure it is robust and reliable with any corrections to the FDAS FPGA or driver software applied.
• A generic configuration for the Harmonic Summing (HSUM) module shall be created and used to determine if it is sufficient to identify a range of pulsar candidates with different frequencies and orbital accelerations.

The Intel Agilex Fourier Domain Acceleration Search (FDAS) FPGA Harmonic Summing Module (HSUM) has been successfully tested to ensure it correctly performs summing of pulsar harmonics and is capable of  identifying pulsar signatures in  a DM (Dispersion Measure) observation. The tested FDAS FPGA version uses a total of three DDR SDRAM interfaces with two storing the Filter Output Plane (FOP) and one storing the DM observation spectrum.

The tests that have been successfully performed are:-

• Simple tests have been carried out to ensure HSUM is correctly selecting and summing the harmonics in a Filter Output Plane (FOP) that has been created using MATLAB scripts. The HSUM module correctly selected and summed the configured FOP locations and reported the threshold crossings, thus proving the Summing Tree architecture. These tests are detailed in Jira story AT4-1062 and also on the PSS Google Drive in:-

PSS Team/FDAS_AGILEX_PI19_RELEASE/AT4-1062_HSUM_SIMPLE_PULSAR_TESTS

https://drive.google.com/drive/folders/1ticyMQRiORYmRpjU34nhYcTWMFLJ17sB

• The Intel Agilex FDAS FPGA has been tested with a time domain observation created in MATLAB (FDAS-HSUM-MID_38d46df_500.0_0.05_1.0_100.397_Gaussian_50.0_123123123.tim) which contains a known accelerating pulsar. This .tim file was Fourier transformed in MATLAB with power level normalisation and passed to the FDAS FPGA as the DM Spectrum Observation in the frequency domain. The FDAS FPGA convoluted the spectrum with a bank of filters in the Convolution (CONV) module configured with the appropriate coefficients to form the Filter Output Plane (FOP). The FOP was then interrogated in the expected locations by the HSUM module and it correctly identified the pulsar signature. These tests are detailed in Jira story AT4-1063 and AT4-1064  also on the PSS Google Drive in:-

PSS Team/FDAS_AGILEX_PI19_RELEASE/AT4-1063_1064_1065_1067_FDAS_TESTED_WITH_TIM_FILE/AT4-1063_1064_COMPARING_ARRIA_VS_AGILEX_WITH_TIM_FILE

https://drive.google.com/drive/folders/1E26dLvjfSO2lDmnkDNY5dasW11GSIOLn

• The Intel Agilex FDAS FPGA testing using the FDAS-HSUM-MID_38d46df_500.0_0.05_1.0_100.397_Gaussian_50.0_123123123.tim time domain observation was then expanded to use a generic configuration for the HSUM module so that it interrogated all possible acceleration rows of the FOP. Essentially HSUM is configured to look everywhere in the acceleration axis of the FOP instead of just looking in the expected locations and thus this is a “real world” test. Again the pulsar signature was identified albeit with a number of “repeats” due to the nature of the search using the generic HSUM configuration, which was expected, and confirms the need for a software sifting algorithm after FDAS to remove repeated pulsar candidates from the candidate list that is passed to the Folding and Optimisation (FLDO) function. These tests are detailed in Jira story AT4-1067  also on the PSS Google Drive in:-

PSS Team/FDAS_AGILEX_PI19_RELEASE/AT4-1063_1064_1065_1067_FDAS_TESTED_WITH_TIM_FILE/AT4-1067_AGILEX_TEST_WITH_FULL_HSUM_CONFIG

https://drive.google.com/drive/folders/1lzctPt1iQaOHcLypcIH0BtDb1AUyxVcu

• The tests FDAS were repeated using the PSS Golden FDAS MATLAB model using the same .tim file and convolution filter coefficients. Good correlation was observed between the Intel Agilex FDAS FPGA and the PSS Golden FDAS MATLAB model, with both correctly identifying the known pulsar. These tests are detailed in Jira story AT4-1065  also on the PSS Google Drive in:-

PSS Team/FDAS_AGILEX_PI19_RELEASE/AT4-1063_1064_1065_1067_FDAS_TESTED_WITH_TIM_FILE/AT4-1065_FDAS_MATLAB_GOLDEN_MODEL

https://drive.google.com/drive/folders/1r97CkweM-YnvbxdkWVn_rbiqaa720Ih8

Although these are only initial tests with an “ideal” input observation, they do indicate the basic operation of the HSUM module in the Intel Agilex FDAS FPGA is operating correctly and that the storing of the FOP in two DDR SDRAMs which operate in unison is also operating correctly.

In addition long term tests were performed to prove that the HSUM module is robust and can continuously process DMs. These tests were successful with HSUM able to process DMs continuously for a 12hr period with 150,000 DMs processed. These tests are detailed in Jira story AT4-1066.

However subsequent testing has shown there is a potential “lock-up” if the user controlled resets are repeatedly applied to the FDAS FPGA. This only occurs on certain builds and even with identical design code a different “seed” (a value to determine where the Intel build of the FPGA image starts) can determine if this problem exists. It appears the problems are related to the DDR Controller and investigation is on-going. However as it is not necessary to apply the resets repeatedly (only normally applied once at power-up)  the FDAS FPGA integration into the Cheetah pipeline can still continue. This “lock-up” scenario is detailed in JIRA ticket AT4-1113 and work on this will need to continue in PI20 to try to further understand the exact cause and resolve the problem.

The FDAS FPGA Design use for these tests (Both the Intel Quartus Build and the Covnetics SVN Repository) is on the PSS Google Drive in:-

PSS Team/FDAS_AGILEX_PI19_RELEASE/FDAS_FPGA_PI19_3_DDR

https://drive.google.com/drive/folders/1dg8nH88CugmUn3RDb7EoUWQpkH1JFG7A

This build uses three DDR SDRAM interfaces, one to store the incoming SD Observation Spectrum and two working in unison to store the FOP.