Benchmark the performance of FDAS Agilex FPGA version using three DDR SDRAM interfaces

In PI17 feature SP-2945 corrections to the two DDR SDRAM version of the FDAS Agilex FPGA  were successfully implemented to ensure PCIe accesses by the Host PC operated correctly. The object of this feature is test and performance-benchmark an FDAS Agilex design version that uses three DDR SDRAM interfaces, with two of the DDR interfaces acting in unison to double the DDR SDRAM access bandwidth of the Convolution (CONV) and Harmonic Summing (HSUM) modules to the Filter Output Plane (FOP). The remaining DDR SDRAM stores the incoming observation data.

The three DDR SDRAM version of the FDAS Agilex FPGA will be derived from the four DDR version that was created in PI16 (with the PCIe corrections applied in PI17 in feature SP-2945) but never tested.

The reason to generate and test this three DDR SDRAM version from the four DDR SDRAM is that it provides a “stepping stone” development approach to reduce the development risk, since it avoids relying on the re-purposing of the fourth DDR SDRAM interface that is normally assigned to an Internal Processor (i.e only make one major change at a time).

This benchmarking will check the following parameters:-

• The time for FDAS to process a DM. It should be possible to compare the three DDR SDRAM Intel Agilex FDAS version to the original Intel Arria 10 FDAS version and the two DDR SDRAM Intel Agilex FDAS version evaluated in SP-3107.
• For a known observation DM data set sent from the PC to the FDAS FPGA via a DMA write over the PCIe check the accuracy of the Filter Output Plane (FOP) which is generated from an observation DM by the Convolution (CONV) module and stored in external DDR SDRAM. The FOP contains 2^22^ x 85 samples each of which is a 32-bit floating point IEEE 754 value. This data can be read back by the host PC via a PCIe DMA access.
• The power consumed by the card that the Intel Agilex FPGA is fitted to.

Given that:-

• In PI16 an FDAS Agilex design using four DDR Interfaces was created to provide enhanced performance
• In PI16 the software to allow communication with the Intel Agilex FPGA family via the PCIe interface was evaluated and proven to work.
• In feature SP-2945 of PI17 corrections were successfully made to the FDAS Agilex design to ensure correct operation of the PCIe accesses.

When A three DDR SDRAM version of FDAS has been created, based on the four DDR SDRAM version and a DM observation is passed by the Host PC to the FDAS FPGA via the PCIe interface and the FDAS FPGA is triggered to process the DM. ** 

Then it shall be possible to benchmark the three DDR SDRAM versions of the Intel Agilex FDAS FPGA. The results should indicate if the three DDR SDRAM version of the Intel Agilex FDAS FPGA is capable of meeting the processing requirements. It should also be possible to compare the three DDR SDRAM Intel Agilex FDAS version to the original Intel Arria 10 FDAS version and the two DDR Intel Agilex FDAS version evaluated in SP-3107.

The Outcomes are:-

1) The Design information for this version of the Intel Agilex FDAS FPGA with three DDR Interfaces (two being used in unison to store the Filter Output Plane "FOP" and one being used to store the incoming DM observation) is available on the PSS Google Drive:-

https://drive.google.com/drive/folders/1qM0HhbhYcMfv-GP1fX7Kq4TUVp8Wl6bI

The Implementation specification detailing the design and the performance is also available in this location and shows that the test results of this three DDR version of the Intel Agilex FDAS FPGA meets the processing time limit of 357ms, with a measured processing time = 253ms. 

2) The software drivers developed in PI16 and PI17 have been enhanced to allow the DM observation to be loaded into the FDAS FPGA from RAM on the Host PC instead of reading a file. This will be required for integration into the PSS Cheetah pipeline.

3) The Intel software driver code was only provided for operation using the Centos Linux distribution. However the software drivers have now been modified so that they will operate with the Ubuntu Linux distribution, which is compatible with PSS Cheetah. The FDAS software driver C code and a description of the software is on the PSS Google drive:

https://drive.google.com/drive/folders/1hCu5LtxWLeUXjiUu0OiXVbzizyMydmEy

4) It has been possible to check that the Convolution of the incoming DM observation is correct by reading the Filter Output Plane from the two DDR SDRAMs where it is stored and comparing the values with a MATLAB model.

5) It has been possible to check the connectivity of the Harmonic Summing Module (HSUM)  to the DDR SDRAMs containing the Filter Output Plane (FOP) by writing unique power values into the FOP and checking that HSUM correctly reports the FOP locations and power values as pulsar candidates. The information for this test and the results is on the PSS Google drive:

https://drive.google.com/drive/folders/1VXuOVdPwFUGwITFEMEE7itIw5s1OTyf8

6) Slides for a demonstration have been prepared and are attached to AT4-1007.