Establish a functional interface between the Intel host software/drivers and the new PSS FDAS design for Agilex FPGAs

In PI15 the FDAS FPGA was translated from the older Intel Arria 10 family to the new higher performance Intel Agilex F family. This translation mainly involved generating the special Intel Agilex IP blocks such as the PCIe Interface block, DDR SDRAM Controller Block and the Fourier Transform Blocks and then modifying the original FDAS circuits to integrate and connect to these new IP blocks.

In PI16 the software that runs on the Host PC to allow communication over the PCIe interface to the Agilex FPGA was evaluated and tested. To perform this task the Agilex FPGA was loaded with an Intel “Reference Design” which contains the PCIe Interface Block and RAMs to store the data from configuration writes and Direct Memory Access (DMA) writes from the Host PC over the PCIe interface. Read-back of this configuration data and DMA data could then be performed by the Host PC over the PCIe Interface to confirm the data has been correctly written into the RAMs in the Intel Agilex FPGA. In this way it was possible to prove that the software running on the PC was operating correctly.

In PI16 an attempt was made to replace the “Reference Design” in the Intel Agilex FPGA with the FDAS design created in PI15. From the initial testing it appeared to be the case that:-

• Read-back of data from the FDAS design to the PC over the PCIe Interface works. This was proven by reading back the Version ID of the FPGA which is hardcoded.
• A configuration write by the PC to the FDAS FPGA over the PCIe interface fails. It actually results in the PC locking up necessitating a re-boot.
• A DMA write by the PC to the FDAS FPGA over the PCIe interface and subsequent DMA read-back fails. This indicates either the DMA write, the DMA read or both fails. The DMA data is stored in the external DDR SDRAMs. It can however be seen via a read-back that the DDR Controller IP blocks have passed calibration.

Hence this feature is to debug the Intel Agilex FDAS FPGA to ensure all the accesses via the PCIe operate correctly. This is likely to involve reviewing the FDAS VHDL design code to locate and fix any bugs. In addition it may be necessary to create test builds which contain an Intel logic analyser called “Signal Tap”, which allows real time monitoring of signals within the FPGA via a PC connected to a USB port on the Intel development card fitted with the Intel Agilex FPGA.

Once the bugs have been identified a fixed the FDAS VHDL code, module simulation test benches, any Intel IP block updates and documentation can be updated and released to the repository for both the FDAS version with two DDR SDRAM interfaces developed in PI15 and the FDAS version with four  DDR SDRAM interfaces developed in PI16.

Given that in PI15 an FDAS design was created for the Intel Agilex FPGA family and in PI16 the software to allow communication with the Intel Agilex FPGA family via the PCIe interface was evaluated and proven to work.

When any bugs in the FDAS FPGA have been identified which prevent communication access via the PCIe interface.

Then it shall be possible to correct the FDAS VHDL code, module simulation test benches, any Intel IP block updates and documentation can be updated and released to the repository. The corrected design can then be used for testing and benchmarking the performance of the FDAS design in the Agilex FPGA family.

The corrections have been made to the  circuits of the two DDR SDRAM version of the Intel Agilex FDAS FPGA to ensure access via the PCIe is possible. In summary the corrections are:-

PCIF Module: Ensure the write_response_valid signal occurs one cycle after the transfer is complete.

PCIe  Transparent Avalon Bridges:-

a) Ensure all address ports are WORD based

b) Remove the BurstCount Signal from the Bridge supporting the PCIe Configuration Interface. 

c) Ensure the Bridges supporting the DMA Write accesses have a waitrequest_allowance of 16 to match that of the PCIe Hard IP Macro

d) Ensure the Bridges supporting the DMA Read requests support 32 pending accesses

PCIe Hard IP Macro: Ensure the address space for the Configuration space is set to 32MBytes - 25 bits

DDRIF2 Module: Modify the FIFOs to accommodate the waitrequest_allowance of 16 of the PCIe Hard IP Macro. 

DDR Controller: Set the DDR SDRAM operating frequency to 1200MHz along with the parameters supplied by Intel in their example design, as Intel have indicated that 1333.333MHz operation is not supported on the Intel Agilex Development Board

This two DDR SDRAM version of the Intel Agilex FPGA has been uploaded to the PSS Google Drive in folder FDAS_AGILEX_PI17_RELEASE:-

Sub-Folder FDAS_PI17_2_DDR_BUILD contains the Quartus Prime build.

Sub-Folder FDAS_PI17_2_DDR_REPOSITORY contains the files for the repository.

This design is being used to benchmark the performance of the Intel Agilex FDAS FPGA in SP-3107 and the performance results shall be added to the above folders.

In addition the corrections described above have been applied to a four DDR SDRAM version of the Intel Agilex FPGA which has been uploaded to the PSS Google Drive in folder FDAS_AGILEX_PI17_RELEASE:-

Sub-Folder FDAS_PI17_4_DDR_BUILD contains the Quartus Prime build.

Sub-Folder FDAS_PI17_4_DDR_REPOSITORY contains the files for the repository.

This four DDR SDRAM version of the Intel Agilex FPGA shall be tested in PI18