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  1. SAFe Program
  2. SP-3152

TDC I&T: Integrate EC with VCC/FSP on one Talon

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    • Obs Mgt & Controls
    • Hide

      The Engineering Console (EC)/BITE/VCC integration directly  with the HPS FSP Control  devices (in a stand alone manner) on an 1-board system, means a gradual integration of components, allowing in this way a more thorough and efficient testing. This represents a stepping-stone towards enabling hardware-in-the-loop testing of the full Mid CBF signal chain on the AA0.5 system.

      Show
      The Engineering Console (EC)/BITE/VCC integration directly  with the HPS FSP Control  devices (in a stand alone manner) on an 1-board system, means a gradual integration of components, allowing in this way a more thorough and efficient testing. This represents a stepping-stone towards enabling hardware-in-the-loop testing of the full Mid CBF signal chain on the AA0.5 system.
    • Hide

      Mid.CBF sunny day auto-correlation scenario is executed and demonstrated in the Mid.CBF development environment, using the MCS software for system startup and VCC signal chain control, but exercising directly the 2 HPS FSP Control devices,  on one TALON-DX board.

      Show
      Mid.CBF sunny day auto-correlation scenario is executed and demonstrated in the Mid.CBF development environment, using the MCS software for system startup and VCC signal chain control, but exercising directly the 2 HPS FSP Control devices,  on one TALON-DX board.
    • 3
    • 3
    • 20
    • 6.667

    • Sub-system Version REL-204 MID CBF MCS v0.7.0

      Sub-system Version REL-280 MID CBF Engineering Console v0.4.0

    • Team_CIPA
    • Sprint 4
    • Hide

      The objective of this feature was to test the HPS FSP Control part of the system, i.e. the `DsFspController` and the `DsFspCorrController`, including their subordinate, low level devices servers (8 device servers in total, controlling the FSP signal processing IP Blocks), using the engineering console (EC). 

      The execution of these integration tests  require the following initialization steps:

      1. Populating the Tango database with all required HPS devices
      2. the loading the bitstream and the HPS device servers onto the Talon boards and starting the servers (by invoking the MCS control.on() command)
      3. And playing back from DDR4 memory test data (LSTVs)
      4. Generating VCC products, which constitute the input to the FSP part of the signal processing chain (by invoking the HPS VccControl.ConfigureScan() and Scan() commands)

      The goal is to execute all preparation steps from the engineering console (EC), then exercise directly the two FSP controllers from the EC (decoupling in this way from the MCS FSP control, ensuring a gradual integration process of sub-components).

      The objective of this feature was attained in two stages as follows:

      1. An additional, intermediate step was added for the testing of the DsFspCorrController.configureScan() command focused on the configuration of the RDT FineChannalizer and DCT devices; namely, instead of using the EC, the signal chain was configured via Pyro in the signal chain verification Jupyter notebooks. This testing approach allowed a more thorough testing/debugging process and easier collaboration with the Firmware engineer in charge (Will Kamp). This testing approach was applied for:
      2. The target approach, integrating EC, BITE and HPS VCC and FSP ( requiring the execution of steps a) to d)  was then used for the DsFspCorrController.Scan() command under story: https://jira.skatelescope.org/browse/CIP-1290.  In addition,  the entire ConfigureScan() sequence (which in particular covers the scope of CIP-1288 and CIP-1270) was retested using this approach.

      All the remaining (support) stories in this feature were also completed:

      https://jira.skatelescope.org/browse/CIP-1273

      https://jira.skatelescope.org/browse/CIP-1310

      https://jira.skatelescope.org/browse/CIP-1333

       

      Show
      The objective of this feature was to test the HPS FSP Control part of the system, i.e. the `DsFspController` and the `DsFspCorrController`, including their subordinate, low level devices servers (8 device servers in total, controlling the FSP signal processing IP Blocks), using the engineering console (EC).  The execution of these integration tests  require the following initialization steps: Populating the Tango database with all required HPS devices the loading the bitstream and the HPS device servers onto the Talon boards and starting the servers (by invoking the MCS control.on() command) And playing back from DDR4 memory test data (LSTVs) Generating VCC products, which constitute the input to the FSP part of the signal processing chain (by invoking the HPS VccControl.ConfigureScan() and Scan() commands) The goal is to execute all preparation steps from the engineering console (EC), then exercise directly the two FSP controllers from the EC (decoupling in this way from the MCS FSP control, ensuring a gradual integration process of sub-components). The objective of this feature was attained in two stages as follows: An additional, intermediate step was added for the testing of the DsFspCorrController.configureScan() command focused on the configuration of the RDT FineChannalizer and DCT devices; namely, instead of using the EC, the signal chain was configured via Pyro in the signal chain verification Jupyter notebooks. This testing approach allowed a more thorough testing/debugging process and easier collaboration with the Firmware engineer in charge (Will Kamp). This testing approach was applied for: https://jira.skatelescope.org/browse/CIP-1288 https://jira.skatelescope.org/browse/CIP-1270 The target approach, integrating EC, BITE and HPS VCC and FSP ( requiring the execution of steps a) to d)  was then used for the DsFspCorrController.Scan() command under story: https://jira.skatelescope.org/browse/CIP-1290 .  In addition,  the entire ConfigureScan() sequence (which in particular covers the scope of CIP-1288 and CIP-1270) was retested using this approach. All the remaining (support) stories in this feature were also completed: https://jira.skatelescope.org/browse/CIP-1273 https://jira.skatelescope.org/browse/CIP-1310 https://jira.skatelescope.org/browse/CIP-1333  
    • 17.6
    • Stories Completed, Integrated, Outcomes Reviewed, Demonstrated, Satisfies Acceptance Criteria, Accepted by FO

    • PI22 - UNCOVERED

    • MID_SUT1 Mid.CBF_SW TDC Team_CIPA

    Description

      Perform partial MCS - HPS FSP integration (for correlation function Mode), with control from the engineering-console (EC). This implies executing successfully, on one Talon board connected to the Linux (Dell) server, the following procedure:

      1. Perform the system setup (bring in all the artefacts from the CAR, load the bitstream, start the servers etc.)  using the EC and the MCS devices dedicated to these tasks (via the CbfControl.on() command)
      2. Run the vcc.ConfigureScan() command to configure the HPS VCC controllers and their subordinate devices.
      3. Generate an LSTV using the EC BITE client
      4. Start the playback of LSTVs  (stored in the DDR4) from the EC BITE client
      5. Run the DsFspContrioller.SetFunctionMode() command
      6. Run the DsFspController.On() command
      7. Run the DsFspCorrController.UpdateDelayModels() command
      8. Run the DsFspCorrController.ConfigureScan() command
      9. Run the DsFspCorrController.Scan() command
      10. Run the DsFspCorrController.EndScan() command
      11. Run the DsFspCorrController.End() command

       

      Ref:  https://confluence.skatelescope.org/display/SE/Mid.CBF+FSP-Part+Control+Design

       

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          Feature - A Feature is a service that fulfills a stakeholder need. Each feature includes a benefit hypothesis and acceptance criteria, and is sized or split as necessary to be delivered by a single Agile Release Train (ART) in a Program Increment (PI). SP-2056 TDC I&T: Integrate MCS with Talon - VCC/FSP Scan

          • Must have - Items labelled as "Must have" are critical to the current delivery timebox in order for it to be a success.
          • Done
          Is delivered by

          Sub-system Version - A version of a sub-system, used in the Release Management and Configuration Management process REL-204 MID CBF MCS v0.7.0

          • Discarded

          Sub-system Version - A version of a sub-system, used in the Release Management and Configuration Management process REL-280 MID CBF Engineering Console v0.4.0

          • Discarded
          mentioned in

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                s.vrcic Vrcic, Sonja
                M.Radulescu Radulescu, Michelle
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                  Story Point Burn-up: (100.00%)

                  Feature Estimate: 3.0

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