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  1. SAFe Program
  2. SP-2056

TDC I&T: Integrate MCS with Talon - VCC/FSP Scan

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    • Obs Mgt & Controls
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      BITE/VCC/FSP integration on the 4-board system will enable hardware-in-the-loop testing of the full Mid CBF signal chain on the AA0.5 system.

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      BITE/VCC/FSP integration on the 4-board system will enable hardware-in-the-loop testing of the full Mid CBF signal chain on the AA0.5 system.
      • 4 Talon DX boards with the Monitoring and Control Software are demonstrated to be running on the Linux server and running the full BITE/VCC/FSP test on the 4-board (antenna) system.
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    • 2.857
    • Team_CIPA
    • Sprint 5
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      The initial goals of this feature were:

      1. Update/test the MCS to support the interface with the 2 new HPS FSP controllers (in both simulation and operational modes)
      2. Update the Engineering Console (EC) and integrate/test the MCS-FSP with the HPS-FSP-Part.
      3. Integrate and test the FSP-part on 4 talon boards.

      These goals have been achieved as follows:

      1. The goal at point 1 was fully achieved
      2. The goal at point 2 was achieved, as the HPS FSP Part was integrated with the MCS devices that have been affected by the updates at point 1) (MCS FSP and FspCorrSubarray devices) with the exception of the integration with the MCS cbfSubarray device (which was not instrumental for this test).
      3. The testing/integration of the FSP-part on 4 talon boards has not been executed due to schedule constraints;

      As a result the MCS FSP part was integrated with the HPS FSP part  to successfully output visibility packets.

      Note that the integration activities in this feature  involved the integration and testing of a large number of Tango devices with the FPGA bitstream:

      • 5 MCS device servers (out of 6) ,
      • 25 HPS device servers 9BITE, VCC and FSP) 
      • a commensurate number of FPGA IP blocks in the bitstream.

      The 3rd goal has not been achieved partly due to objective reasons (for example, team members having to take time off due to illness and 2 team members working for the first time on the MCS SW) and party due to upfront underestimation of effort required. This included unforeseen difficulties occurring in the process of integrating such a large number of devices/components. 

      A number of stories which were related to goal 3 ( integration/testing on 4-boards) or that did not affect directly the main objectives of this feature have been differed to PI18; these are: 

      https://jira.skatelescope.org/browse/CIP-1255

      https://jira.skatelescope.org/browse/CIP-1293

      https://jira.skatelescope.org/browse/CIP-1304

       

      Note also that due to an unstable Talon-board and recent upgrades to a new Linux kernel the feature could not be fully demonstrated during the System DEMO session; however, screen-captures and logs illustrating the successful capture of visibilities from the internal (rehearsal) demo have been attached to story  https://jira.skatelescope.org/browse/CIP-1137).

      Show
      The initial goals of this feature were: Update/test the MCS to support the interface with the 2 new HPS FSP controllers (in both simulation and operational modes) Update the Engineering Console (EC) and integrate/test the MCS-FSP with the HPS-FSP-Part. Integrate and test the FSP-part on 4 talon boards. These goals have been achieved as follows: The goal at point 1 was fully achieved The goal at point 2 was achieved, as the HPS FSP Part was integrated with the MCS devices that have been affected by the updates at point 1) (MCS FSP and FspCorrSubarray devices) with the exception of the integration with the MCS cbfSubarray device (which was not instrumental for this test). The testing/integration of the FSP-part on 4 talon boards has not been executed due to schedule constraints; As a result the MCS FSP part was integrated with the HPS FSP part  to successfully output visibility packets. Note that the integration activities in this feature  involved the integration and testing of a large number of Tango devices with the FPGA bitstream: 5 MCS device servers (out of 6) , 25 HPS device servers 9BITE, VCC and FSP)  a commensurate number of FPGA IP blocks in the bitstream. The 3rd goal has not been achieved partly due to objective reasons (for example, team members having to take time off due to illness and 2 team members working for the first time on the MCS SW) and party due to upfront underestimation of effort required. This included unforeseen difficulties occurring in the process of integrating such a large number of devices/components.  A number of stories which were related to goal 3 ( integration/testing on 4-boards) or that did not affect directly the main objectives of this feature have been differed to PI18; these are:  https://jira.skatelescope.org/browse/CIP-1255 https://jira.skatelescope.org/browse/CIP-1293 https://jira.skatelescope.org/browse/CIP-1304   Note also that due to an unstable Talon-board and recent upgrades to a new Linux kernel the feature could not be fully demonstrated during the System DEMO session; however, screen-captures and logs illustrating the successful capture of visibilities from the internal (rehearsal) demo have been attached to story   https://jira.skatelescope.org/browse/CIP-1137 ).
    • 17.6
    • Stories Completed, Integrated, Outcomes Reviewed, Demonstrated, Satisfies Acceptance Criteria, Accepted by FO
    • PI24 - UNCOVERED

    • MID_SUT1 Mid.CBF_SW SYSTEM_DEMO_5 TDC Team_CIPA

    Description

      Updates MCS and Engineering Console (and Talon DX HPS software as required) to implement VCC/FSP scan commands on the hardware setup with 4 Talon DX boards connected to the Linux (Dell) server.

      Ref: https://confluence.skatelescope.org/display/SE/MCS-Talon+Integration

       

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                s.vrcic Vrcic, Sonja
                M.Radulescu Radulescu, Michelle
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                Feature Progress

                  Story Point Burn-up: (100.00%)

                  Feature Estimate: 7.0

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                  Complete1236.0
                  Total1236.0

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