Mid.CBF Hardware Refresh Agilex investigation - Part 3

There could be substantial power saving for Mid.CBF by moving to latest generation FPGAs for the larger SKA correlators (AA2 - AA4).  This investigation needs to happen fairly quickly in order to have time to implement changes if that direction is selected.

• A 400GE tester IP that can:
  • manage the Intel segmented 400GE MAC interface
  • achieve close to line rate throughput.
• Checked into gitlab
• Trial synthesis passing in CI, meetings the expected timing targets.
• Tests passing in CI.
• Demonstrated ability to configure and control the tester and observe the results on the switch.

• Designed 400GE Tester FPGA for COTS investigation based on 54 instances of the SPFRx packetizer. Tester can achieve 400GE line rate. 
• Design is working on Intel Agilex I-Series Development Board hardware.
• Simulation and synthesis jobs are passing in NRC Gitlab:
• Developed control script and configuration scenarios for the COTS investigation based on the proposed architecture.
• Developed P4 program and runtime configuration for the test switch to test the FSP switch program.
• Developed P4 program and runtime configuration for the FSP switch.
• Demonstrated 400GE Tester FPGA, Test P4 program, and FSP P4 program together at OMC ART System Demo 16.4. Attached demo slides here.

OMC ART System Demo 16.x (2).pdf