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  1. SAFe Program
  2. SP-2345

Frequency Slice Input Buffer IP Design / Implement / Test

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    • Feature
    • Should have
    • PI14
    • None
    • Obs Mgt & Controls
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      TDC AA0.5/AA1 correlation bitstream requires the Frequency Slice Input Buffer to sync resampling and fine channelization processing to the input rate of Frequency Slice packets for each receptor from the VCC stage.

       

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      TDC AA0.5/AA1 correlation bitstream requires the Frequency Slice Input Buffer to sync resampling and fine channelization processing to the input rate of Frequency Slice packets for each receptor from the VCC stage.  
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      1. High level design of IP block is complete with interfaces and register set defined and reviewed.
      2. FS Input Buffer IP block is implemented and reviewed.
      3. FS Input Buffer test bench is developed and all tests pass.
      4. IP block and test bench firmware and committed to NRC gitlab.
      Show
      High level design of IP block is complete with interfaces and register set defined and reviewed. FS Input Buffer IP block is implemented and reviewed. FS Input Buffer test bench is developed and all tests pass. IP block and test bench firmware and committed to NRC gitlab.
    • 3
    • 3
    • 3
    • 1
    • Team_CIPA
    • Sprint 4
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      • The entity description and the register set were reviewed by the Mid.CBF firmware team.
      • The design was coded and the code was reviewed. 
      • A testbench was developed, covering a variety of scenarios including single packet drops, packet errors, and dropout/resync test cases. All tests are passing in gitlab CI.
      • Trial Synthesis is passing in gitlab CI.
      • All artifacts committed to gitlab. 
      Show
      The entity description and the register set were reviewed by the Mid.CBF firmware team. The design was coded and the code was reviewed.  A testbench was developed, covering a variety of scenarios including single packet drops, packet errors, and dropout/resync test cases. All tests are passing in gitlab CI. Trial Synthesis is passing in gitlab CI. All artifacts committed to gitlab. 
    • 14.4
    • Stories Completed, Outcomes Reviewed, Satisfies Acceptance Criteria, Accepted by FO

    • PI22 - UNCOVERED

    Description

      The TALON Asynchronous design does not have FPGA clocks that are locked to the sample clocks in the digitizer at each DSH.  The means that TDC VCC processing cannot simply process a set number of samples in the DSH stream per "N" clock cycles in the FPGA.

      The FS Input Buffer performs a number of functions:

      1.  Stores a small number of VCC packets from the VCC data stream in a circular buffer in on-chip memory.  Index where a given packet is written into the circular buffer is based on the Timestamp and PSN of the VCC packet.
      2. Reads packets from the circular buffer at a rate that matches the write rate and produces a stream of samples to subsequent signal processing IP blocks.
      3. Detects missing packets and inserts flagged samples into the stream of samples.

       

       

       

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          Feature - A Feature is a service that fulfills a stakeholder need. Each feature includes a benefit hypothesis and acceptance criteria, and is sized or split as necessary to be delivered by a single Agile Release Train (ART) in a Program Increment (PI). SP-2210 Wideband Input Buffer IP Design / Implement / Test

          • Should have - Items labelled as "Should have" are important but not necessary for delivery in the current delivery timebox. While "Should have" items can be as important as "Must have", they are often not as time-critical or there may be another way to satisfy the requirement so that it can be held back until a future delivery timebox.
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                b.alachkar Alachkar, Bassem
                S.Harrison Harrison,Stephen
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                Feature Progress

                  Story Point Burn-up: (100.00%)

                  Feature Estimate: 3.0

                  IssuesStory Points
                  To Do00.0
                  In Progress   00.0
                  Complete1027.0
                  Total1027.0

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