Wideband Input Buffer IP Design / Implement / Test

The TALON Asynchronous design does not have FPGA clocks that are locked to the sample clocks in the digitizer at each DSH.  The means that TDC VCC processing cannot simply process a set number of samples in the DSH stream per "N" clock cycles in the FPGA.

The DSH Wideband Input Buffer performs a number of functions:

1.  Stores a small number of packets from the DSH data stream in a circular buffer in on-chip memory.  Index where a given packet is written into the circular buffer is based on the Timestamp and PSN of the DSH packet.
2. Reads packets from the circular buffer at a rate that matches the write rate and produces a stream of samples to subsequent signal processing IP blocks.
3. Detects missing packets and inserts flagged samples into the stream of samples.

  See the Wideband Input Buffer section of the following document for more details:

https://docs.google.com/document/d/1BOvJGdngMPfrpXRZkbT54sCxYZJoQympwX18v-54Wzg/edit?usp=sharing