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  1. SAFe Program
  2. SP-2014

Create testbenches using the MCCS verification framework.

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Details

    • Feature
    • Must have
    • PI12
    • None
    • Obs Mgt & Controls
    • Hide

      VHDL simulations are implemented that are run whenever the firmware CI pipeline is triggered. This will provide an indication of the likelihood of the firmware successfully deploying on real hardware.

      Show
      VHDL simulations are implemented that are run whenever the firmware CI pipeline is triggered. This will provide an indication of the likelihood of the firmware successfully deploying on real hardware.
    • Hide

      VHDL simulator(s) are implemented and are run when new firmware is committed to the firmware repository.

      Show
      VHDL simulator(s) are implemented and are run when new firmware is committed to the firmware repository.
    • 1.5
    • 1.5
    • 13
    • 8.667
    • Team_MCCS
    • Sprint 5
    • Hide

      On-boarding of new developers was undertaken with this feature.

      This feature was to start to integrate the VHDL verification framework into the CI pipeline.

      The PI11 FIFO test bench work was integrated into the CI pipeline, to be triggered by a merge.

      The antenna buffer architecture verification was then refactored for integration into the CI pipeline. Two scopes of testing, "full" and "reduced", were defined. CI integration was specified such that a merge to main/dev branches would trigger the "full" tests and routine merge/commit to any other branch would trigger the "reduced" tests.

      Show
      On-boarding of new developers was undertaken with this feature. This feature was to start to integrate the VHDL verification framework into the CI pipeline. The PI11 FIFO test bench work was integrated into the CI pipeline, to be triggered by a merge. The antenna buffer architecture verification was then refactored for integration into the CI pipeline. Two scopes of testing, "full" and "reduced", were defined. CI integration was specified such that a merge to main/dev branches would trigger the "full" tests and routine merge/commit to any other branch would trigger the "reduced" tests.
    • 12.6
    • Stories Completed, Integrated, Outcomes Reviewed, Satisfies Acceptance Criteria, Accepted by FO

    Description

      Currently no VHDL simulations are performed as part of the firmware CI pipeline. The VHDL verification framework should be leveraged and integrated in the CI pipeline. The work will be firstly carried out on a specific VHDL module (TBD) and should include different verification strategies, as already supported by the verification environment. As simulations might be time-consuming, several strategies are used to address different operations on the repository. In this context a merge to master or dev branch in the firmware repository should  trigger the "full" strategy, while commit/merge to other branch should trigger "reduced" strategy.

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          relates to

          Feature - A Feature is a service that fulfills a stakeholder need. Each feature includes a benefit hypothesis and acceptance criteria, and is sized or split as necessary to be delivered by a single Agile Release Train (ART) in a Program Increment (PI). SP-1633 Alveo Firmware Code in Gitlab

          • Must have - Items labelled as "Must have" are critical to the current delivery timebox in order for it to be a success.
          • Done

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                v.mohile Mohile, Vivek
                r.braddock Braddock, Ralph
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                Feature Progress

                  Story Point Burn-up: (100.00%)

                  Feature Estimate: 1.5

                  IssuesStory Points
                  To Do00.0
                  In Progress   00.0
                  Complete712.0
                  Total712.0

                  Dates

                    Created:
                    Updated:
                    Resolved:

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