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  1. SAFe Program
  2. SP-1289

TALON Infrastructure - develop software components to facilitate communication with FPGA

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    • Feature
    • Not Assigned
    • PI8
    • None
    • Obs Mgt & Controls
    • Hide

      The completion of the TALON-DX Board Support Package is critical to users of the TALON-DX board.  These users include:

      1. CIPA team developing TALON Demonstration Correlator (TDC)
      2. DSH SPFRx Team developing Band 1/2 Digitizer prototype

      The purpose of this feature is to provide a development environment and tools to translate the firmware IP block register set  (which defines the interface between software and firmware)  to  TANGO API (attributes), to provide means for a TANGO Device to obtain the base address for the firmware IP Block register set, and facilitate access to register sets, so that TANGO Devices/Servers in Linux user space can use Linux system calls to access FPGA registers. 

      Show
      The completion of the TALON-DX Board Support Package is critical to users of the TALON-DX board.  These users include: CIPA team developing TALON Demonstration Correlator (TDC) DSH SPFRx Team developing Band 1/2 Digitizer prototype The purpose of this feature is to provide a development environment and tools to translate the firmware IP block register set  (which defines the interface between software and firmware)  to  TANGO API (attributes), to provide means for a TANGO Device to obtain the base address for the firmware IP Block register set, and facilitate access to register sets, so that TANGO Devices/Servers in Linux user space can use Linux system calls to access FPGA registers. 
    • Hide

      FPGA can be successfully re-configured with different or the same bitstream.

      After bit stream re-configuration software running in user space can obtain the base address for the firmware IP block it monitors and controls, and can access the registers to read and write content. 

      Developers and user guides updated for the latest version of software are available, code is well documented.

      Show
      FPGA can be successfully re-configured with different or the same bitstream. After bit stream re-configuration software running in user space can obtain the base address for the firmware IP block it monitors and controls, and can access the registers to read and write content.  Developers and user guides updated for the latest version of software are available, code is well documented.
    • 5
    • 5
    • Team_CIPA
    • Sprint 5
    • Hide

      The test application fpga-mgr was modified so as to provide a CLI that would allow a user to interactively load JSON files into the RegisterSetBase class and then interactively inspect which register sets were loaded into the class and what the contents of each register set got set to.

      Several different JSON files were created and used in the test. After each file was loaded in the RegisterSetBase class was inspected and found to have all of the register sets defined in the JSON file with each register set containing the correct settings of the values contained in each one.

      Currently on the https://gitlab.drao.nrc.ca/SKA/util/Libraries/registersetbase/-/tree/AT5-459-90p-code-review branch of the registersetbase repo.

      Implementing partial reconfiguration from HPS software was not completed this PI and stories have been moved to SP-1298 which will be done in PI10, unless there is capacity to do more work in PI9 as planning progresses.

      Show
      The test application fpga-mgr was modified so as to provide a CLI that would allow a user to interactively load JSON files into the RegisterSetBase class and then interactively inspect which register sets were loaded into the class and what the contents of each register set got set to. Several different JSON files were created and used in the test. After each file was loaded in the RegisterSetBase class was inspected and found to have all of the register sets defined in the JSON file with each register set containing the correct settings of the values contained in each one. Currently on the https://gitlab.drao.nrc.ca/SKA/util/Libraries/registersetbase/-/tree/AT5-459-90p-code-review branch of the registersetbase repo. Implementing partial reconfiguration from HPS software was not completed this PI and stories have been moved to SP-1298 which will be done in PI10, unless there is capacity to do more work in PI9 as planning progresses.
    • 8.6
    • Stories Completed, Integrated, Outcomes Reviewed, Satisfies Acceptance Criteria, Accepted by FO
    • PI22 - UNCOVERED

    • TALON-Infra

    Description

      TALON infrastructure provides the development environment and tools to translate the firmware IP block register set  (which defines the interface between software and firmware)  to TANGO API (attributes), this is used as the starting point for development of TANGO devices that control and monitor firmware. The purpose of this feature is to develop software infrastructure  which provides means for a TANGO Device to obtain the base address for the firmware IP Block register set (for each instance of IP block within the programmed FPGA bitstream) and to facilitate access to  firmware registers, so that TANGO Devices/Servers running  in  the  Linux user space can use Linux system calls to access FPGA registers. 

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                v.alberti Valentina Alberti
                m.pleasance Pleasance, Michael
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                Feature Progress

                  Story Point Burn-up: (100.00%)

                  Feature Estimate: 5.0

                  IssuesStory Points
                  To Do00.0
                  In Progress   00.0
                  Complete210.0
                  Total210.0

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