TDC FSP FW - Corner-turn Investigation

The intent of the TALON Demonstration Correlator (TDC) is to have a correlator on the sky using the TALON hardware and Frequency Slice Architecture (FSA) signal processing algorithms. TDC will be used for early integration with  DISH, TMC and SDP.  Mid.CBF DDD and Test Specification define the hi-level BITE architecture;  BITE firmware and software developed for TDC will be fully re-used for Mid.CBF.

Investigation into DDR4 performance for corner turn operations are important to determine a final implementation for TDC and SKA Mid.CBF. 

The baseline design for the corner turn prior to correlation relies on synchronous "per-antenna" processing across the entire Mid.CBF system such that samples that need to be correlated (same "time" at phase center of the sub-array") are generated by the Mid.CBF processing pipeline synchronously in order to group multiple antennas together prior to writing data into the corner turn.  This investigation focuses on determining if a corner turn design can be implemented that can handle asynchronous "per-antenna" processing by writing data for each antenna independently into the corner turn.  This will allow the corner turn to perform both the corner turn and data alignment operations and increase the flexibility of the correlator design be removing dependence on clock and 1PPS signals locked to the central time reference.

Tasks:

1) Investigation / implementation of on-chip RAM pre-corner turn

2) Investigation / simulation of DDR4 performance for corner turn 720 Byte cell with random write / sequential read sequence.

3) Generate report on feasibility of the proposed "asynchronous" corner turn