TALON Infrastructure - communication between HPS and FPGA - Memory Mapping, DeTrI, tools

Each TALON-DX Board is equipped with Intel Stratix 10 Soc (FPGA and ARM processor, a.k.a. Hardened Processor System - HPS, on the same silicon die). Stratix-10 provides two busses for communication between the HPS and FPGA, hi-performance Avalon bus and light-wait Avalon bus. The FPGA bitstream consists of many firmware IP blocks, each implementing a specific function. Each firmware IP block provides a set of registers that can be used to configure, control and monitor firmware, in addition, when needed a whole memory block may be transferred from software to firmware (or vice versa).
TDC team design a custom solution for communication between application software (running in the Linux user space) and FPGA firmware IP blocks (registers), to enable efficient and reliable mapping between software and firmware. Initial idea was to represent each firmware IP block as a Linux device, and use a standard Unix method for communication with firmware IP blocks.
The purpose of this enabler is to investigate an alternative solution (direct memory mapping), develop a prototype and measure performance. Results of the preliminary investigation and prototyping are promising, but more work is required.
(DeTri / tools / memory mapping)

This feature is limited in scope to developing a prototype(s) to

1. Add a JSON representation output to the DeTrI address map script to describe the memory map.
2. Investigate the use of AXI response codes (i.e. DECERR) to signal addressing errors to the userspace software.
   1. Supposedly, the DECERR raises an ARM data-abort exception in the CPU, that linux will handle and send a signal (maybe SIGBUS) to the offending process that can trap it and then raise an exception up the software/Tango stack.
3. transition from Avalon memory mapped implementation to AXI4. Should offer further performance improvements, especially with clock domain crossings in the register bus.

To investigate -

1. performance improvements for reading, by optimising reading of bulk data - hopefully simultaneously increasing data transport speed and reducing blocked CPU time.
2. implement burst read and write on the HPS2FPGA high-performance bridge. This is a firmware modification and may double the throughput, and reduce blocking CPU time.