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  1. SAFe Program
  2. SP-3803

Plan and start the integration of an FPGA FDAS module into the PSS pipeline

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    • Enabler
    • Should have
    • PI21
    • COM PSS SW
    • None
    • Data Processing
    • Hide

      See Why? in description

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      See  Why?  in description
    • Hide

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    • 15
    • 15
    • 0
    • Team_PSS
    • Sprint 5
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      All the acceptance criteria for this enabler have been met and are described in this document: https://docs.google.com/document/d/1D79uIsdDriTms1zTbrDV6qsinF0MAc4FqodqPL2fjS0/edit?usp=sharing

      In addition, we have been able to build Intel libraries via cmake and use them in a basic unit test from within panda. The relevant code has now been merged:
      MR for changes to the FDAS FPGA interface
      MR for Building Intel FPGA libraries using CMake in Panda

      Show
      All the acceptance criteria for this enabler have been met and are described in this document: https://docs.google.com/document/d/1D79uIsdDriTms1zTbrDV6qsinF0MAc4FqodqPL2fjS0/edit?usp=sharing In addition, we have been able to build Intel libraries via cmake and use them in a basic unit test from within panda. The relevant code has now been merged: MR for changes to the FDAS FPGA interface MR for Building Intel FPGA libraries using CMake in Panda
    • 21.6
    • Stories Completed, Outcomes Reviewed, Satisfies Acceptance Criteria, Accepted by FO
    • PI22 - UNCOVERED

    • Low G4

    Description

      https://confluence.skatelescope.org/display/SE/Integrate+an+FPGA+FDAS+component+into+the+PSS+pipeline 

      Who?

      • PSS Product Tester; PSS Developer

       

      Why?

      • This work will enable the developers of PSS to integrate the FPGA FDAS code into the PSS pipeline (Cheetah), based on detailed information about the design of the FDAS module's interfaces with Cheetah.
      • When integrated in future PIs, FPGA FDAS will be used in end-to-end product tests with test vectors, which will enable verification of PSS functional and performance requirements for a wide range of pulsar search use cases.

      What?

      • The aim of this Goal is to deliver a detailed design and definitions of the FPGA FDAS interfaces, and begin the integration of the FPGA FDAS code into the PSS pipeline (Cheetah) by writing the unit tests.
      • Following the delivery of the design, the existing FPGA-based FDAS software will be integrated into Cheetah by implementing the detailed design. This will enable a PSS user to run a Cheetah pipeline that uses the FPGA-based pulsar search code.

       

      Success Metrics

      • Agree on a detailed design for the interfaces between the FPGA FDAS firmware code and the Cheetah interface code:
      • Decide on the memory management of the FPGA FDAS input and output objects (memory pages)
      • Decide on the object structure of the FPGA FDAS input and output objects (Fourier spectra & candidate lists)
      • Define the internal control layer within Cheetah needed to interact with the FPGA FDAS code
      • PI21 stretch:
        • Write unit tests for the Cheetah interfaces to FPGA FDAS

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                A.Noutsos Noutsos, Aristeidis
                A.Noutsos Noutsos, Aristeidis
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                Feature Progress

                  Story Point Burn-up: (100.00%)

                  Feature Estimate: 15.0

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                  In Progress   00.0
                  Complete1386.0
                  Total1386.0

                  Dates

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                    Updated:
                    Resolved:

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