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  1. SAFe Program
  2. SP-3635

Mid CBF PST Beamformer Firmware Design part 2

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      In addition to enabling development of the feature backlog toward AA1, design work on the PST beamformer at this stage will help firmware team members ramp up to support current and future firmware development and testing.

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      In addition to enabling development of the feature backlog toward AA1, design work on the PST beamformer at this stage will help firmware team members ramp up to support current and future firmware development and testing.
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      • All PST beamformer firmware GitLab repositories created for IP blocks, associated design modules, and signal models.
      • PST beamformer firmware GitLab repositories updated with design documentation sufficient to allow IP block development and testing.
      • PST FPGA Persona setup in GitLab with top level PST VHDL checked in for build with Test Vector Generator and Packetiser blocks.
      • PST Test Vector Generator IP and PST Packetiser blocks:
        • Detailed design documented in GitLab.
        • Test Vector Generator implemented and checked into GitLab.
        • Initial minimal function working Packetiser implemented and checked into GitLab.
        • Initial simulation testbenches running to verify typical operation.
        • Designs built into PST FPGA bitstream (stretch objective)
        • Verified on Talon-DX Mid.CBF hardware by capturing PST UDP packets on server (stretch objective)
      • Control software interface specification documented, including sequence diagrams to capture dynamic behavior.
      • Firmware testing via the control software interface specified and documented.
      Show
      All PST beamformer firmware GitLab repositories created for IP blocks, associated design modules, and signal models. PST beamformer firmware GitLab repositories updated with design documentation sufficient to allow IP block development and testing. PST FPGA Persona setup in GitLab with top level PST VHDL checked in for build with Test Vector Generator and Packetiser blocks. PST Test Vector Generator IP and PST Packetiser blocks: Detailed design documented in GitLab. Test Vector Generator implemented and checked into GitLab. Initial minimal function working Packetiser implemented and checked into GitLab. Initial simulation testbenches running to verify typical operation. Designs built into PST FPGA bitstream (stretch objective) Verified on Talon-DX Mid.CBF hardware by capturing PST UDP packets on server (stretch objective) Control software interface specification documented, including sequence diagrams to capture dynamic behavior. Firmware testing via the control software interface specified and documented.
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    • Team_CIPA
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      Top level PST bitstream persona and top level of PST processing hierarchy created in GitLab: https://gitlab.drao.nrc.ca/SKA/Mid.CBF/FW/persona/tdc_vcc_pst_processing All PST IP blocks repositories created in GitLab: https://gitlab.drao.nrc.ca/SKA/Mid.CBF/FW/ip/pstc_ch4k.git https://gitlab.drao.nrc.ca/digital-systems/fpga/blocks/tst_vector_gen.git https://gitlab.drao.nrc.ca/digital-systems/fpga/blocks/pst_sync_buffer.git https://gitlab.drao.nrc.ca/digital-systems/fpga/blocks/pst_beam_summer.git https://gitlab.drao.nrc.ca/digital-systems/fpga/blocks/pst_packetiser.git Software register interfaces defined and documented in GitLab repositories Minimal implementation completed to output initial PST packets (Test Vector Generator and PST Packetizer). Initial Bitstream created and verified it meets timing. No hardware functional testing done.    
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    • Stories Completed, Outcomes Reviewed, Accepted by FO

    • PI24 - UNCOVERED

    • Mid.CBF_HW Team_CIPA

    Description

      Implementing the minimum possible in order to output valid formed PST UDP packets to the SDP by implementing the PST Test Vector Generator and PST Packetiser IP blocks of the PST processing signal chain. Provides an initial working partial design for Mid-CBF software and the SDP teams to work with. Provides the framework to be able to do incremental updates and verification to implement the full PST processing chain for AA1.

      Mid CBF AA1 functionality

      • TDC architecture (correlator and beamforming firmware sized for up to 8 receptors)
      • 8 receptors, 8 talon boards:
      • Talon boards 1-4 each with the same BITE/VCC with FSP correlation bitstream
      • Talon boards 5-8 each with the same BITE/VCC with FSP PST beamforming bitstream
      • Bands 1 and 2 - supported under AA0.5
      • 800 MHz of imaging correlation bandwidth - supported under AA0.5
      • 1 sub-array
      • 800 MHz PST beamforming for one beam on boresight

      will require the following FPGA IP blocks:

      • PST Test Vector Generator
      • PST Channelizer IP block (done but not tested)
      • PST Sync buffer IP block
      • PST Beam summer IP block
      • PST Packetizer IP block

      plus bitstream integration and testing, including signal chain modeling and verification (ref: hardware_testing_notebooks).

      This feature is intended to cover the initial design documentation of the IP blocks for the PST beamformer firmware for AA1, including development of associated Python signal models. 

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              Adam.Avison Avison, Adam
              R.Huxtable Huxtable, Robert
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