Multi-Receptor Correlator Signal Chain Testing

This feature was completed with total success. Talon board to board communications across the SLIM network optical links were tested and shown to be "error free" when properly configured.  Furthermore, when the optical transceivers (the mid-board optics - LEAP modules) were de-tuned to generate sporadic bit errors, the FPGA firmware was shown to tolerate the subsequent errored, lost, merged or fractured packets. The Packet Stream Repair (PSR) firmware replaces the corrupted data with 'flagged' data such that samples correctly flow into the resampler/delay tracker (RDT) with monotonically increasing timestamps.  Some deficiencies in the PSR firmware were found and corrected. Multi-board correlation was also shown to work using the BITE data generator. Up to 4  talon boards were configured with BITE generating identical Gaussian noise signals on the X-polarisation (same seed) and independent signals on the Y-Polarisation. The polarisation coupler was used to introduce a different proportion of the X-pol into the Y-pol signals for each receptor. Each receptor was given a different sampling rate for the offset-clocking scheme used. Multiple FSP were also configured, with 200 MHz bandwidth being processed on each talon board, for a total of 800 MHz BW. The visibilities from each FSP are collected across the SLIM to be transmitted on a single 100GbE interface. The correlator was configured to generate visibilities for up to 6 baselines plus 4 auto-correlations. The RDT converted (resampled) the signals to a common sample rate and the corner turner successfully aligned the signals removing the bulk transport delay. This resulted in near perfect correlation efficiency for the XX-pol visibilities of each baseline as expected. The XY/YX-pol visibilites showed the proportions of X coupled into each Y signal, and YY-pol visibilies showed the product of X-pol coupled into each receptors Y-pol signal. Linear High Order Delay Models (HODM) were introduced to the system. First different delay models were introduced to the BITE generated data. When correlated without correcting the delay this resulted in fringe patterns to the visibilities captured, present in the time and frequency domains. When the opposite delay model is loaded into the FSP RDT, then the delay is successfully removed - eliminating the fringe pattern seen. This work was completed in the Jupyter Notebook hardware testing environment.