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  1. SAFe Program
  2. SP-3427

Mid CBF PST Beamformer Firmware Design part 1

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      In addition to enabling development of the feature backlog toward AA1, design work on the PST beamformer at this stage will help firmware team members ramp up to support current and future firmware development and testing.

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      In addition to enabling development of the feature backlog toward AA1, design work on the PST beamformer at this stage will help firmware team members ramp up to support current and future firmware development and testing.
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      • All PST beamformer firmware GitLab repositories created for IP blocks, associated design modules, and signal models.
      • PST beamformer firmware GitLab repositories updated with design documentation sufficient to allow IP block development and testing.
      • Python signal models developed and tested. 
      • Control software interface specification documented, including sequence diagrams to capture dynamic behaviour.
      • Firmware testing via the control software interface specified and documented.
      Show
      All PST beamformer firmware GitLab repositories created for IP blocks, associated design modules, and signal models. PST beamformer firmware GitLab repositories updated with design documentation sufficient to allow IP block development and testing. Python signal models developed and tested.  Control software interface specification documented, including sequence diagrams to capture dynamic behaviour. Firmware testing via the control software interface specified and documented.
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    • Team_CIPA
    • Sprint 5
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      The initial AA1 PST beamformer firmware design was completed and captured in:

      Complementary PST control software documentation is contained in Mid CBF AA1 PST Software. Python signal models were not developed since the signal processing aspect of the PST AA1 is somewhat trivial (single boresight beam). 

      Show
      The initial AA1 PST beamformer firmware design was completed and captured in: Mid CBF AA1 PST Firmware Confluence page, including links to GitLab repositories for the IP blocks containing documentation, interface specifications, and test benches. ska-mid-cbf-pst-proto ReadTheDocs with software preliminary interface specification and dynamic behaviour, especially HPS low level devices , and HPS VCC top level to low level devices . Complementary PST control software documentation is contained in Mid CBF AA1 PST Software . Python signal models were not developed since the signal processing aspect of the PST AA1 is somewhat trivial (single boresight beam). 
    • 19.6
    • Stories Completed, Solution Intent Updated, Outcomes Reviewed, Demonstrated, Satisfies Acceptance Criteria, Accepted by FO

    • PI24 - UNCOVERED

    • Mid.CBF_HW Team_CIPA

    Description

      Mid CBF AA1 functionality

      • TDC architecture (correlator and beamforming firmware sized for up to 8 receptors)
      • 8 receptors, 8 talon boards:
      • Talon boards 1-4 each with the same BITE/VCC with FSP correlation bitstream
      • Talon boards 5-8 each with the same BITE/VCC with FSP PST beamforming bitstream
      • Bands 1 and 2 – supported under AA0.5
      • 800 MHz of imaging correlation bandwidth – supported under AA0.5
      • 1 sub-array
      • 800 MHz PST beamforming for one beam on boresight

      will require the following FPGA IP blocks:

      • PST Channelizer IP block (done but not tested)
      • PST Sync buffer IP block
      • PST Beam summer IP block
      • PST Packetizer IP block

      plus bitstream integration and testing, including signal chain modeling and verification (ref: hardware_testing_notebooks).

      This feature is intended to cover the initial design documentation of the IP blocks for the PST beamformer firmware for AA1, including development of associated Python signal models. 

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                Adam.Avison Avison, Adam
                R.Huxtable Huxtable, Robert
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                Feature Progress

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                  Feature Estimate: 6.0

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