Commission PCIe Extended Message Signalled Interrupts (MSI-X) and Configuration via PCIe for PSS FDAS on Agilex FPGA and eliminate timing warnings in the FDAS build

• The PCIe MSI-X (Message Signalled Interrupts) will improve the overall processing times as the FDAS FPGA shall automatically indicate to the PC when it has finished processing a DM, instead of the host software having to periodically interrogate FDAS
• The CvP (Configuration via PCIe) allows for easy upgrades in the future without the need to manually access each board and also allows the FPGA to be re-imaged to perform a completely different task.
• The elimination of timing warnings in the Intel Quartus build of the FDAS FPGA ensures there is no possibility of reset removal causing unwanted behaviour in the logic circuits.

• For MSI-X:
  • The MSI-X interrupts have been commissioned, so that the Host PC will know when the FDAS FPGA has completed its processing via the reception of an MSI-X interrupt.
• For CvP:
  • The FDAS “image” (.sof file ) has been spilt into a “periphery image”(.pof file) for the PCIe and an “image” (.rbf file) for just the FDAS processing circuits.
  • It is possible to load the PCIe “periphery image” (.pof file ) into the Flash memory on the Intel Agilex Development Board Flash memory. When the board powers up this PCIe “periphery image” shall automatically be loaded into the FPGA to establish the PCIe interface and then the “image” (.rbf file) containing the FDAS processing circuits can be downloaded from the Host PC via the PCIe interface to establish a fully functional Intel Agilex FDAS FPGA.
• For timing warning elimination:
  • The Intel Quartus build of the Intel Agilex FDAS FPGA shall be clear of any timing warnings, test benches (i.e. unit tests) shall still pass the the FDAS FPGA shall still operate correctly when tested on the Intel Agilex Development board.

In this feature we updated driver and API code to the latest code supplied by Intel in Quartus 23.2 and implemented MSI-X in application software. All code is available here: https://drive.google.com/drive/folders/1Oaj6087CQXxYh5I7EfnXoF46_vjejTNg?usp=drive_link 

In addition, we successfully downloaded the “periphery image” to established the PCIe interface of the FPGA and then downloaded the FDAS processing circuit “image” to the FPGA via the PCIe interface. Software and hardware files are available here: https://drive.google.com/drive/folders/1YfY6gQxJBINtTK-HwZrjDUk74I5_UMGy?usp=drive_link 

In addition, we modified reset distribution in the CONV module, HSUM module and the PCIe domain, the build is now free from any timing warnings or failures. The three DDR version (two DDR SDRAMs acting in unison storing the FOP, and one DDR SDRAM storing the incoming spectrum) of the Intel Agilex FDAS FPGA is available here: https://drive.google.com/drive/folders/1B7nJXlmM6XB_aWoz5dLQqJLkgrG9hevx 

More detail is given below in the outcomes for each story:-

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AT4-1138
Code changes in Intel driver and APIs from Quartus 22.4 to 23.2 have been incorporated into the development software. Changes required for correct operation with Ubuntu 22.4 have been maintained.The application software has been successfully re-run following the changes.

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AT4-1139
When MSI-X is enabled, the application software will wait after triggering FDAS processing and then continue when User MSI-X is correctly received.

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AT4-999
Following download of "periphery image" (.jic file) to flash memory on the Intel Agilex Development Board and it's subsequent loading into the Agilex FPGA during boot. The PCIe information received with the Linux command "lspci", indicates the design is loaded correctly.

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AT4-1000
The core image (.rbf file) can be correctly downloaded from the Host PC via the PCIe interface to the Agilex FPGA using the downstream CvP diver supplied by Intel.

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AT4-1123
With modified reset distribution in the CONV module, HSUM module and the PCIe domain and wth the FDAS  .qsf (Build file) and .sdc (Timing constraint file) updated accordingly, the build is free from any timing warnings or failures.