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  1. SAFe Program
  2. SP-3143

Mid CBF talon board startup and self test firmware

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    • Feature
    • Should have
    • PI17
    • None
    • Obs Mgt & Controls
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      Create an initial BIST FPGA firmware to be auto loaded on power-on that provides hardware testing features for the Talon-board.

      Also use for an initial talon_board/LRU assembly factory test.

      Show
      Create an initial BIST FPGA firmware to be auto loaded on power-on that provides hardware testing features for the Talon-board. Also use for an initial talon_board/LRU assembly factory test.
    • Hide

      Bitstream created that exercises the hardware interfaces (SLIM, DDR4, Ethernet, I2C, ...).

      Show
      Bitstream created that exercises the hardware interfaces (SLIM, DDR4, Ethernet, I2C, ...).
    • 3
    • 3
    • 0
    • Team_CIPA
    • Sprint 5
    • Hide

      See OMC ART PI17.6 Demo : https://confluence.skatelescope.org/display/SE/2023-02-23+OMC+ART+System+Demo+17.6

      Source bitstream and scripts can be found under:
      /shared/talon-dx-utilities/verification/talon/talon-dx-bist/

      Source scripts:
      digital-systems / talon-dx / software / applications / talon-dx-bist · GitLab (nrc.ca)

      Documentation to run tests:
      Talon-DX Bootup Built-In Self Tests (BIST) - Software Engineering - SKAO Community Confluence (skatelescope.org)

      Running of BIST on bootup shown at 17.6 Demo

      Show
      See OMC ART PI17.6 Demo : https://confluence.skatelescope.org/display/SE/2023-02-23+OMC+ART+System+Demo+17.6 Source bitstream and scripts can be found under: /shared/talon-dx-utilities/verification/talon/talon-dx-bist/ Source scripts: digital-systems / talon-dx / software / applications / talon-dx-bist · GitLab (nrc.ca) Documentation to run tests: Talon-DX Bootup Built-In Self Tests (BIST) - Software Engineering - SKAO Community Confluence (skatelescope.org) Running of BIST on bootup shown at 17.6 Demo
    • 17.6
    • Stories Completed, Demonstrated, Satisfies Acceptance Criteria, Accepted by FO

    • PI24 - UNCOVERED

    • Team_CIPA

    Description

      Create a Built in Self Test (BIST) image for the FPGA - a new persona on top of tdc_base.

      This will be automatically loaded at power-on by a script.

      The BIST image will provide testing interfaces for:

      • SLIM links - check Error rate (internal loopback, with external loopback cables). Can use existing SLIM FW.
      • DDR4 interfaces. Exercise the DDR4 EMIF with test patterns - report errors. Either new FW required to do this, or update https://gitlab.drao.nrc.ca/SKA/Mid.CBF/FW/ip/ddr4_tester (dropped during planning due to time)
      • Clocks - use the existing talon_status module.
      • 100G Ethernet - check error rate. (internal loopback, ) Check Ethernet IP registers to establish successful link, lock and word alignment.

      The accompanying script (probably Python) should also test that the I2C connected components respond. Maybe just an address scan on the i2c bus and check what responds.
      Script should display progress and success on the front panel LEDs (4 Red/Green LEDs).

       

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          relates to

          Epic - Created by Jira Software - do not edit or delete. Issue type for a big user story that needs to be broken down. SS-100 Mid Digital Signal Chain Processing for AA0.5

          • Must have - Items labelled as "Must have" are critical to the current delivery timebox in order for it to be a success.
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                Adam.Avison Avison, Adam
                W.Kamp Kamp, Will
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                  Feature Estimate: 3.0

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