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  1. SAFe Program
  2. SP-2817

TDC AA0.5/AA1 Correlation FW integration (part 4)

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      Integration of FW IP blocks for the TDC AA0.5/AA1 correlation bitstream to verify the end-to-end signal chain coordination and synchronisation across interconnected talon boards.

       

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      Integration of FW IP blocks for the TDC AA0.5/AA1 correlation bitstream to verify the end-to-end signal chain coordination and synchronisation across interconnected talon boards.  
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      1. New firmware IP blocks are integrated into the TDC AA0.5/AA1 correlation bitstream as they are available:
        • SLIM transceivers.
      2. Resource usage and timing reports are generated
      3. Timing closure issues are identified and plans created for future PIs.
      4. Firmware can be configured to produce cross-correlation visibilities from multiple receptor sources (BITEs).
      Show
      New firmware IP blocks are integrated into the TDC AA0.5/AA1 correlation bitstream as they are available: SLIM transceivers. Resource usage and timing reports are generated Timing closure issues are identified and plans created for future PIs. Firmware can be configured to produce cross-correlation visibilities from multiple receptor sources (BITEs).
    • 5
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    • 5
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    • Sub-system Version REL-234 SIGNAL-CHAIN-MID v0.2.0

    • Team_CIPA
    • Sprint 3
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      AC1. SLIM transceivers successfully integrated into the bitstream and configured to achieve very low bit-error rates (lower than measurable in overnight tests). This took quite some effort to find the correct settings of the many knobs in the FPGA transceivers and LEAP mid-board-optics modules to achieve this.

      AC2. For a 4-board correlator configuration the resource usage is:

      • 52% ALMs.
      • 46% RAM blocks
      • 58% DSP blocks
      • 16 Transceivers (8 for 2x100GbE, 8 for SLIM meshes)

      AC3. Timing closure issues were identified and solved. Bitstream successfully meets timing constraints. FPGA clocks running at final full performance.

      AC4. Using the pyro hardware testing python code we can configure and run BITE data through a multi-board correlator and get the expected visibility magnitudes produced and delivered in SPEAD packets over the 100GbE interface.
      Due to hardware availability (and power supply issues) can demonstrate this currently for two boards/receptors, producing two auto-correlation baselines and one cross-correlation baselines. Code will support addition of 2 more boards when available.

      Sunny day functionality achieved. Detailed analysis of the produced visibilities can be done in PI17.

       See OMC ART System Demo 16.6.

      Show
      AC1. SLIM transceivers successfully integrated into the bitstream and configured to achieve very low bit-error rates (lower than measurable in overnight tests). This took quite some effort to find the correct settings of the many knobs in the FPGA transceivers and LEAP mid-board-optics modules to achieve this. AC2. For a 4-board correlator configuration the resource usage is: 52% ALMs. 46% RAM blocks 58% DSP blocks 16 Transceivers (8 for 2x100GbE, 8 for SLIM meshes) AC3. Timing closure issues were identified and solved. Bitstream successfully meets timing constraints. FPGA clocks running at final full performance. AC4. Using the pyro hardware testing python code we can configure and run BITE data through a multi-board correlator and get the expected visibility magnitudes produced and delivered in SPEAD packets over the 100GbE interface. Due to hardware availability (and power supply issues) can demonstrate this currently for two boards/receptors, producing two auto-correlation baselines and one cross-correlation baselines. Code will support addition of 2 more boards when available. Sunny day functionality achieved. Detailed analysis of the produced visibilities can be done in PI17.  See OMC ART System Demo 16.6 .
    • 16.6
    • Stories Completed, Integrated, Outcomes Reviewed, Demonstrated, Satisfies Acceptance Criteria, Accepted by FO

    Description

      This feature is to integrate and prove the "sunny day" functionality of a multiple talon-board correlator.

      This will build on the currently tested MVP firmware build and python testing environment that currently generates one auto-correlation baseline for a single antenna.

      • Integrate and tune the SLIM transceivers to establish stable links between FPGA.
      • Python/Jupyter functionality to statically configure BITE and datapaths on multiple talon boards.
      • Generate, capture and analyse cross-correlation visibilities.

      Update firmware modules as required for monitoring and control points.

      Fix any bugs.

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          Sub-system Version - A version of a sub-system, used in the Release Management and Configuration Management process REL-234 SIGNAL-CHAIN-MID v0.2.0

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                b.alachkar Alachkar, Bassem
                S.Harrison Harrison,Stephen
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                  Feature Estimate: 5.0

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