HPS FSP: Top Level Control

This development will implement the HPS FSP top level control of the signal processing chain and will integrate it with all the FSP low level  Tango device servers that control the FPGA IP blocks in the FSP_Part. The ConfigureScan/GotToIdle and the Scan/EndScan commands workflow will be demonstrated by executing tests natively, in the gitlab pipeline.

HPS code repositories updated, including test drivers and test cases as appropriate. Documentation updated to reflect the functionality implemented under this feature. Successful demonstration of the HPS FSP ConfigureScan()/GotToIdle() and Scan()/EndScan() commands workflows demonstrated. 

The following new HPS FSP Control (client) devices have been implemented (as per  the [FSP Control design |  https://confluence.skatelescope.org/display/SE/Mid.CBF+FSP-Part+Control+Design ),]  test harness generated (including multiple custom tests), tested and reviewed: Base class for the DsFsp<FunctionMode>Controller devices:  https://gitlab.drao.nrc.ca/digital-systems/ska-mid-cbf/software/libraries/ska-mid-talondx-fsp-base  (which includes an observational state model)  DSFSpController device:  https://gitlab.drao.nrc.ca/digital-systems/ska-mid-cbf/software/applications/ska-mid-cbf-fsp-app/-/tree/cip-1133-fsp-corr-controller/src/ds-fsp-controller ; This included in addition to the observatinal command (ConfigureScan() Scan() EndScan(), End()) support  for periodically updating the delay models and ireintialization of the Resampler-and-delay-tracker and Corner-turner via puublish-subscribe communication with respective low level devices. DsFspCorrController (client device to low level HPS DSs): ( https://gitlab.drao.nrc.ca/digital-systems/ska-mid-cbf/software/applications/ska-mid-cbf-fsp-app/-/tree/master/src/ds-fsp-corr-controller Multiple low level devices have been updated as  identified to be required by the FSP design ; ;] this includes addition/modification of selected commands/attributes, commensurate updates to the test harness, updates to align to the newest HPS DS repo structure and testing activities: Resampler-and-Delay-Tracker (RDT) DS:  https://gitlab.drao.nrc.ca/digital-systems/software/applications/ds-resampler-delay-tracker/-/tree/develop DDRT Corner-Turner (DCT) DS:  https://gitlab.drao.nrc.ca/digital-systems/software/applications/ds-dct/-/tree/develop VCC DS:  https://gitlab.drao.nrc.ca/digital-systems/software/applications/ds-vcc/-/tree/develop Fine Channalizer DS: https://gitlab.drao.nrc.ca/digital-systems/software/applications/ds-fine-channelizer/-/tree/develop