Proof of concept of simulation of the execution of the IDG microbenchmark with SST

• KR1: Confluence page describing the use of the SST framework, the models used, the simulation results and perspectives for a basic simulation of a microbenchmark
• KR2 (uncommitted): comparison of simulation results to benchmark measurements on a given machine
• KR2: demo of the use of SST

Part of the work corresponding to this feature has moved to SP-3020 because:

• studying IDG is mostly interesting if the behaviour of GPUs can be simulated (which we are not yet able to achieve with SST)
• focus has moved to looking at data transfers because they impact the SDP's interconnect

Still the following results have been achieved as part of SP-2608:

• installation and use of SST and SSTmacro has been achieved,
• on very basic MPI hello-world code:
  • simple models of the inter-node interconnect have been produced,
  • off-line simulation based on execution traces collected with dumpi was carried out (with limited results due to the simplicity of the code),
• finding accurate and detailed information on the interconnect of the Jean-Zay machine in order to model it to compare simulation results to benchmarks proves very difficult as this information is not public.

As a result the focus has moved to trying to simulate the imaging-iotest benchmark and on carrying out a sensitivity analysis of the simulation results (ie. to what extent do results vary with the network model used). Examining the quality of these results in an absolute sense will be left for later for a machine whose hardware details can be obtained (possibly Grid5000).