Develop system tests of the AA0.5 PST voltage recorder components in CI

Provides automated end-to-end testing of the AA0.5 PST signal chain (data capture, shared buffer and disk writer modules). Prepares PST for integration tests with CBF hardware at the PSIs and with simulated or real data streams from CBF simulators/array verification systems.

• PST's RECV, SMRB and DSP.DISK components deployed in a Kubernetes environment on PSI infrastructure.
• End-to-end CI tests of the PST processing for AA0.5 demonstrated with simple CBF simulators.
• End-to-end manual tests of real CBF data streams demonstrated (if available).

The DSP.DISK, RECV and SMRB software components have been assembled into a helm deployment that provides the initial release of the PST C++ signal processing software required for AA0.5.  The release includes a simple CBF simulator that fills packets with a repeatable pseudo-random sequence of bits, and a data validator that verifies that the expected pseudo-random sequence is received and written to disk.

Initial integration between the PST Beam TANGO device and the RECV, SMRB and DSP components has also been completed. This demonstrates the first vertical integration from the PST-LMC control commands right through to the C++ signal processing software, and provides the basis for testing the AA0.5 Use Cases for PST in PI17.

Releases for all of the PST software components have been drafted (see AT3-319) and a demonstration of the software has been scheduled for DP System Demo 17.1.