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Type: Feature
Priority: Must have
Fix Version/s: PI18
Component/s: MID CBF
Labels:
- Mid.CBF_HW
- Team_CIPA

ARTs:

Obs Mgt & Controls
Benefit hypothesis:

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Integration of the end-to-end signal chain for one receptor / one frequency slice will reduce the risk of integration during TDC AA0.5 Build 1.

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Integration of the end-to-end signal chain for one receptor / one frequency slice will reduce the risk of integration during TDC AA0.5 Build 1.
Acceptance criteria:

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TDC MVP1 test plan is executed and tests pass.
DDR4 is added to the BIST bitstream, tests run.

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TDC MVP1 test plan is executed and tests pass. DDR4 is added to the BIST bitstream, tests run.
Feature Points:
7
Initial Size:
7
Cost of Delay:
40
WSJF:
5.714
Delivered By:

REL-234 SIGNAL-CHAIN-MID v0.2.0
Epic Link:
AA0.5 MID Digital Signal Chain Processing
Agile Teams:

Team_CIPA
Due Sprint:
Sprint 5
Story Point Burn-up:
Overdue:
Outcomes:

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The breadth of tests envisioned in this feature were achieved, however in the attempt many small issues were teased out and fixed. The application of a single frequency tone to the system is a very stringent test, with any deviation immediately obvious in the visibilites as power is detected in channels adjacent to the expected channel.

This testing raised issues that were not detectable in previous testing with random gaussian noise. This has been been very valuable in perfecting the signal processing firmware blocks and the BITE long-sequence-test-vector generation.

A more detailed account of the outcomes from the single tone testing is in story CIP-1039

Show
The breadth of tests envisioned in this feature were achieved, however in the attempt many small issues were teased out and fixed. The application of a single frequency tone to the system is a very stringent test, with any deviation immediately obvious in the visibilites as power is detected in channels adjacent to the expected channel. This testing raised issues that were not detectable in previous testing with random gaussian noise. This has been been very valuable in perfecting the signal processing firmware blocks and the BITE long-sequence-test-vector generation. A more detailed account of the outcomes from the single tone testing is in story CIP-1039
Resolved PI.Sprint:
18.6

Feature Checklist:

Stories Completed, Outcomes Reviewed, Satisfies Acceptance Criteria, Accepted by FO

Requirement Status:

PI24 - UNCOVERED
Labels_MIRO:
Mid.CBF_HW Team_CIPA

Description

Build and execute the next batch of tests (Tests 1.1 through 5.1.) from the TDC MVP1 test plan https://docs.google.com/document/d/1js9GotiAZjzNFSav-br-vwgs24xtmOmLjqkGOoFIA9c/edit?usp=sharing

The tests are largely focused on verifying the resampling and delay tracking functionality, and sub channel channeliser frequency response.

The aim is to check that the signal chain is implemented correctly, can be programmed to correctly, and there are no unexpected deviations from the specifications.

These tests will be executed in the "python pyro notebook" environment.

Also

Add DDR4 Testing to the Build-In-Self-Test (BIST) to verify that the three External Memory Interfaces (EMIFs) and DDR4 RAM sticks are working well at power on. This will require some special FPGA firmware to execute the DDR memory tests. It will be added to a special BIST bitstream that is loaded on power-on.

Attachments

Issue Links

Is delivered by

REL-234 SIGNAL-CHAIN-MID v0.2.0

Discarded

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Structure

Activity

People

Assignee:: Alachkar, Bassem

Reporter:: Harrison,Stephen

Votes:: 0 Vote for this issue

Watchers:: 1 Start watching this issue

Feature Progress

Story Point Burn-up: (100.00%)

Feature Estimate: 7.0

	Issues	Story Points
To Do	0	0.0
In Progress	0	0.0
Complete	5	26.0
Total	5	26.0

Dates

Created:: 10/Mar/22 9:13 PM

Updated:: 15/Apr/24 9:44 AM

Resolved:: 30/May/23 9:01 AM

TDC MVP1 Build 1 - Execute Test Plan (Part 3)