PSS FPGA FDAS: Confirm via simulation that the Intel Agilex Floating Point Adder IP and RAM declarations incorporated in PI13 provide the correct functionality in the FFT Harmonic Summing module for acceleration searches.

In order to create an FDAS image suitable to be loaded into an Agilex FPGA the HSUM module requires a new Agilex IP Floating Point  Adder to replace the Arria 10 IP. In addition RAMs with different clock rates on the A and B ports have to be coded differently to comply with Agilex requirements. These changes were identified and made in PI13 when the Agilex performance study was performed. However it needs to be confirmed via simulation that these changes have been performed correctly.