PSS FPGA FDAS: Implement the new Reset release IP function required by the Intel Agilex FPGA family (implement Intel guidelines AN891)

 In order to create an FDAS image suitable to be loaded into an Agilex FPGA the design needs to be adapted to use special Intel Reset IP. The Agilex family uses new IP components (FFTs etc) and also supports “Hyperflex” technology to reduce the interconnect delays between elements in the design all of which  substantially improve performance. The new IP components and “Hyperflex” technology requires a special reset strategy which Intel provide via their Reset IP.