PSS FPGA FDAS: Increase the internal data bus width of the PCIe-to-external DDR4 SDRAM memory from 256-bits to 512-bits to match the internal interface of the Intel Agilex PCIe IP

From the study undertaken in PI13 the Intel Agilex family appears to have superior performance to the Arria 10 family used by the current FDAS design and hence should improve processing times . As the Intel Agilex PCIe supports 16  lanes with internal 512-bit buses  (compared to 256-bit in Arrial 10) the bandwidth is improved, however DDRIF2 module has to be modified to support this wider bus.

Given that the PCIe Hard Macro IP Block DMA interface is changing from a 256-bit data interface (in Intel Arria 10) to a 512-bit data interface (in Intel Agilex).

When the DDRIF2 module has been redesigned to support 512-bit data interfaces to the  PCIe Hard IP macro and the DDR Controller and Calibration block have been placed in a VHDL wrapper.

Then the DDRIF2 module shall have a compatible interface to transfer data between the PCIe Macro and the external DDR4 SDRAM, ready to be included neatly in the FDAS Top Level structure along with the Wrapper for the DDR Controller/Calibration block

The FDAS DDRIF2 module  has been modified to support the 512-bit data interfaces from the PCIe Hard IP Macro and tested using the updated test bench. In addition the Intel Agilex DDR Controller and Calibration blocks have been placed in a VHDL wrapper to allow easy instantiation in the FDAS Top Level structure. The design information is on the PSS Google drive in the "FDAS_AGILEX_PI14_RELEASE" folder and an associated document "FDAS Agilex PI14 Release Directory Structure_2.pdf"describes the sub-folders within the "FDAS_AGILEX_PI14_RELEASE" folder to allow easy identification of the desired files. The issue status of the "FDAS Agilex PI14 Release Directory Structure_2.pdf" will increase as further FDAS  information is released during PI14.