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  1. SAFe Program
  2. SP-2385

PSS FPGA FDAS: Add MSI-X (Extended Message Signal Interrupts) to the FDAS PCIe (interface from the system to the FPGA card) using the Intel Agilex PCIe IP

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    • Feature
    • Could have
    • PI14
    • COM PSS SW
    • None
    • Data Processing
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      From the study undertaken in PI13 the Intel Agilex family appears to have superior performance to the Arria 10 family used by the current FDAS design and hence should improve processing times . Interrupts are required for fast signalling to the Host PC and  it is necessary  for the FDAS FPGA to support MSI-X as the legacy MSI protocol used in the Arria 10 implementation is not supported in the Intel Agilex family.

      Show
      From the study undertaken in PI13 the Intel Agilex family appears to have superior performance to the Arria 10 family used by the current FDAS design and hence should improve processing times . Interrupts are required for fast signalling to the Host PC and  it is necessary  for the FDAS FPGA to support MSI-X as the legacy MSI protocol used in the Arria 10 implementation is not supported in the Intel Agilex family.
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      Given that the Intel Agilex FPGA family PCIe Hard Macro IP Block only  supports MSI-X (Extended Message Signaling Interrupts) instead of legacy MSI in the Intel Arria 10 FPGA family.

      When the FDAS FPGA MSIX module has been designed and verified in VHDL, with associated address space decoding provided by the modified FDAS MCI-TOP module

      Then the FDAS FPGA in Agilex technology shall support message signal interrupts to inform the Host software when convolution and harmonic summing tasks have completed.

      Show
      Given  that the Intel Agilex FPGA family PCIe Hard Macro IP Block only  supports MSI-X (Extended Message Signaling Interrupts) instead of legacy MSI in the Intel Arria 10 FPGA family. When  the FDAS FPGA MSIX module has been designed and verified in VHDL, with associated address space decoding provided by the modified FDAS MCI-TOP module Then  the FDAS FPGA in Agilex technology shall support message signal interrupts to inform the Host software when convolution and harmonic summing tasks have completed.
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    • Team_PSS
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      The FDAS MSIX module has been created to support the Extended Message Signalled Interrupts (MSI-X) from the  FDAS FPGA to the Host PC. The MSI-X Interrupts are used to inform the Host PC when the processing within the FDAS FPGA has completed. A test bench has been created and successfully run for the MSIX module and a design document has been created . In addition the MCI_TOP and CTRL module have been updated to provide address decode space in the FPGA memory map to allow the new MSIX module to be configured. The test benches for the MCI_TOP and CTRL modules have been updated and successfully run.  The design documentation for the MCI_TOP and CTRL modules have been updated accordingly. The design information is on the PSS Google drive in the "FDAS_AGILEX_PI14_RELEASE" folder and an associated document "FDAS Agilex PI14 Release Directory Structure_4.pdf"describes the sub-folders within the "FDAS_AGILEX_PI14_RELEASE" folder to allow easy identification of the desired files. 

      Show
      The FDAS MSIX module has been created to support the Extended Message Signalled Interrupts (MSI-X) from the  FDAS FPGA to the Host PC. The MSI-X Interrupts are used to inform the Host PC when the processing within the FDAS FPGA has completed. A test bench has been created and successfully run for the MSIX module and a design document has been created . In addition the MCI_TOP and CTRL module have been updated to provide address decode space in the FPGA memory map to allow the new MSIX module to be configured. The test benches for the MCI_TOP and CTRL modules have been updated and successfully run.  The design documentation for the MCI_TOP and CTRL modules have been updated accordingly. The design information is on the PSS Google drive in the " FDAS_AGILEX_PI14_RELEASE " folder and an associated document " FDAS Agilex PI14 Release Directory Structure_4.pdf "describes the sub-folders within the " FDAS_AGILEX_PI14_RELEASE " folder to allow easy identification of the desired files. 
    • 14.6
    • Stories Completed, Outcomes Reviewed, Satisfies Acceptance Criteria, Accepted by FO
    • PI22 - UNCOVERED

    Description

      In order to create an FDAS image suitable to be loaded into an Agilex FPGA the design needs to be adapted to accept the Intel Agilex family PCIe (Peripheral Component Interconnect Express)  IP as it is different to the IP that has been used in the existing FDAS  Arria 10 FPGA. The new Agilex family PCIe supports MSI-X (Extended Message Signal Interrupts) instead of the legacy MSI and as a consequence the FDAS MSI module needs to me modified to support MSI-X. 

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              A.Noutsos Noutsos, Aristeidis
              L.Levin-Preston Levin-Preston, Lina
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              Feature Progress

                Story Point Burn-up: (100.00%)

                Feature Estimate: 4.0

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