PSS FPGA FDAS: Update the PCIe (interface from the system to the FPGA card) of the FDAS FPGA to increase the bandwidth from eight lanes to 16 lanes using the Intel Agilex PCIe IP

From the study undertaken in PI13 the Intel Agilex family appears to have superior performance to the Arria 10 family used by the current FDAS design and hence should improve processing times . The PCIe shall support 16 lanes instead of eight in the existing FDAS  Arria 10 FPGA, and hence shall have a greater bandwidth.

The PCIe Hard Macro design created using the Intel Quartus Prime software Platform Designer shall be complete with Gen 4 x 16 lanes bandwidth and the ports to support MSI-X Message Signaled Interrupts. The PCIe Hard Macro shall be ready to be instantiated in the FDAS Top Level Structure.

The PCIe Hard IP Macro for the FDAS has been created in the Agilex FPGA family with Gen 4 x 16 lane bandwidth and supports the MSI-X Message Signalled Interrupts. The PCIF module has also been updated to interwork correctly with the new PCIe Hard IP Macro. The design information is on the PSS Google drive in the "FDAS_AGILEX_PI14_RELEASE" folder and an associated document "FDAS Agilex PI14 Release Directory Structure_2.pdf"describes the sub-folders within the "FDAS_AGILEX_PI14_RELEASE" folder to allow easy identification of the desired files. The issue status of the "FDAS Agilex PI14 Release Directory Structure_2.pdf" will increase as further FDAS  information is released during PI14.