PSS FPGA FDAS: Update Convolution module for Intel Agilex FPGA

From the study undertaken in PI13 the Intel Agilex family appears to have superior performance to the Arria 10 family used by the current FDAS design and hence should improve processing times . The upgraded CONV module is required to allow the FDAS FPGA to be tested in a Commercial Off the Shelf (COTS) card fitted with an Agilex FPGA.

The CONV module design (untested) shall be complete with Intel Agilex FFTs, IFFTs and DSP block IP and with necessary modifications to support back-pressure from the DDR SDRAMs as in Agilex the FFT once commenced cannot be paused.  The CONV design VHDL code and Agilex IP shall be up-loaded to the PSS Google Drive.

The Intel Quartus Prime IP for the FFT (Fast Fourier Transform) / IFFT (Inverse Fast Fourier Transform)  and floating point multipliers (also with add/subtract) have all been generated for the Intel Agilex family.

Unlike the Intel Arria 10 family FFT/IFFTs, the Agilex family does not provide a signal to indicate when a 1024 point FFT/IFFT has completed and also unlike Arria 10, Agilex does not allow an FFT/IFFT to pause midway through its processing. This has required design changes to the CONV module as it affects back-pressure operation when the downstream DDR4 SDRAM cannot accept more data. The solution has been to create a pulsed signal that provides an indication when an FFT/IFFT has finished based on the "vaild" signal generated by the FFT/IFFT  and also to only allow an FFT/IFFT to commence when it is known that there is sufficient storage space in CONV module's local output data store. 

The design information is on the PSS Team Google drive in the "FDAS_AGILEX_PI14_RELEASE" folder and an associated document "FDAS Agilex PI14 Release Directory Structure_4.pdf"describes the sub-folders within the "FDAS_AGILEX_PI14_RELEASE" folder to allow easy identification of the desired files.