SLIM Hardware Integration and Testing

Integration of the correlator is the next step towards end-to-end processing and will reduce the risk of integration during TDC AA0.5 Build 1.  The SLIM IP is required to transmit data between FPGAs in TDC and must be verified on hardware prior to integration of TDC MVP1 Build 1.

SLIM FW integrated with the stratix10 Transceiver in native-phy mode using the enhanced PCS functionality to implement the 64/66b block-alignment, scrambling, and gearboxing.
Integration FW setup to instantiate up to 56 SLIM transceivers across 5 Mid-Board-Optics (MBOs) on the Talon-DX board. This is implemented as the "talon_dx-tdc_base-interface_test" persona bitstream.
Previously developed Tango SW updated and integrated into an engineering GUI.
Demoed connection between two Talon-DX boards using 12 lanes of one MBO over a physical fibre cable at 25.78125 Gbps each. This showed that the SLIM FW was functioning correctly, with links uniquely identified with different idle control words.
Discovered some additional work needed to optimise the transceiver analog parameters to eliminate bit errors.