Correlator IP Tango Device and Visibility Transport FW

Integration of the correlator is the next step towards end-to-end processing and will reduce the risk of integration during TDC AA0.5 Build 1.  The sync buffer is the next component in the signal chain after the fine channel packetizer and optical interconnect.

Correlator (X-part) firmware state machines were updated to support the TDC/AA1 firmware integration where 20 fine channels are correlated simultaneously (for 8 receptors) giving each FPGA 200 MHz of correlation BW.  The full SKA1 configuration will do a single channel at a time, 10 MHz BW per FPGA for 200 receptors.

Visibility output formatting and packetisation is implemented as per the current CSP-SDP ICD - i.e. SPEAD with 35 byte visibility records per baseline. Each FPGA will output 744 SPEAD streams, each consisting of heaps with 36 baselines * 20 channels as a 2 dimensional array. Four FPGA will provide the full 800MHz correlated BW for AA0.5/AA1.

Visibility packetisation implemented as two firmware modules.

1. visibility_packetiser which performs visibility formatting and SPEAD packet creation.
2. visibility_pkt_streams_to_ethernet which aggregates SPEAD packets from several sources (FPGA) to a single 100GbE connection, adding appropriate UDP/IP/Ethernet headers.

Trial synthesis of these modules (synthesised on the Stratix10 FPGA independently) gives the following resource usage and maximum operating frequencies (Fmax).

visibility_packetiser
==== Resource Usage ====
ALMs 4673.5
ALMs used for memory 150
M20Ks 28
DSP Blocks 19
==== Performance =======
-------- Fmax Summary –
i_clk 510.73 MHz 
Comfortably meets required clock rate >= 390 MHz.

visibility_pkt_streams_to_ethernet - 4 stream merge (sized for AA0.5)
==== Resource Usage ====
ALMs : 4652.9
ALMs used for memory: 210
M20Ks : 65
DSP Blocks : 0
==== Performance =======
-------- Fmax Summary –
i_clk : 417.89 MHz
Meets Requires required clock rate >= 390 MHz. Although more headroom would be beneficial.

Tango Device Servers were written for the HPS to configure the correlator long term accumulator (LTA) firmware, which controls the reading out of data from the correlator, and either accumulating it, or dumping it to the visibility packetiser. The Tango Device takes a JSON configuration string as input, interprets it to write an entry into the LTA DDR4 external memory for each baseline and channel configuration. The entries and their order instruct the firmware when to dump visibilities and in what order.

These modules are the last in the chain for an end-to-end minimum processing FPGA bitstream, and are ready for integration in a future PI.