Combine and document Python code to generate VHDL register interface

AC 1 - procedures to read and write to register sets ****************************************************** As realised by MCCS-418: Version 1.0.0 of the user guide has been generated as html in the Firmware repository in 'Firmware/modules/common/testbench_example/docs/doc_build'. It covers the major elements of the testing framework: the python toolset 'VUnit', the VHDL testbench and the python script to drive the tests. It explains individual VUnit features and links to code in the accompanying example testbenches. A user has followed the configuration steps in the guide to run the examples themselves. Firmware repo MR: https://www.ict.inaf.it/gitlab/SKA/ska_lfaa_firmware/-/merge_requests/23 AC2.- ready to be used for writing testbenches ************************************************* As realised through MCCS-417: An example VUnit FIFO testbench has been created, edited and pushed to the firmware repository in 'Firmware/modules/common/testbench_example'. It demonstrates all our highlighted features for the testing framework. A python script is provided which performs the necessary set up and drives the testbench, and it has been checked out and ran by several users. Through the review stage we decided to make the stimuli and checker into more generic components which can be reused in other tests, and they have now been moved into axi4_lib ('axi4/src/vhdl/tb/sims'). To support the testbench template and example, MCCS-605 provides a demonstartion of using Axi4lite testbench for testing. MCCS-607 presents an example of using Axi4lite which shows how to access XML2VHDLgenerated memory-maps which calls upon the guidance authored through this feature. Completing this feature a pythin only project had been prepared which can be pip installed which allows XML2VHDL to be installed directly: pip install git+ https://bitbucket.org/ricch/xml2vhdl.git