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ARTs:

Obs Mgt & Controls
Benefit hypothesis:
- Prepare timing synchronisation solution for Low.CBF
- Program P4 switch to act in PTP “Boundary Clock” mode
- Write a P4 program to route PTP packets
- Distribute PTP timing packets to Alveo cards
Acceptance criteria:
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P4 configured in PTP boundary mode

P4 switch sends PTP traffic from internal chipset to Tofino ASIC

Provided response to PTP ECP

Demonstrated PTP traffic flow using both Linux and Alveo capture
Show
P4 configured in PTP boundary mode P4 switch sends PTP traffic from internal chipset to Tofino ASIC Provided response to PTP ECP Demonstrated PTP traffic flow using both Linux and Alveo capture
Feature Points:
1
Initial Size:
1
WSJF:
13
Epic Link:
CSP-Low Roadmap
Agile Teams:

Team_PERENTIE
Due Sprint:
Sprint 4
Story Point Burn-up:
Overdue:
Outcomes:

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https://docs.google.com/presentation/d/1H_2LD8WzYRR1kcSOrryetIkr_hbDUfvHZ5qOpiMJmsg/edit#slide=id.gbad7b2301b_2_15

Show
https://docs.google.com/presentation/d/1H_2LD8WzYRR1kcSOrryetIkr_hbDUfvHZ5qOpiMJmsg/edit#slide=id.gbad7b2301b_2_15
Resolved PI.Sprint:
10.4

Feature Checklist:

Stories Completed, Integrated, Outcomes Reviewed, Demonstrated, Satisfies Acceptance Criteria, Accepted by FO

Develop a Perentie System Timing Synchronisation solution

relates to

SP-1387 Timing Synchronisation

mentioned in: Page Loading...; Page Loading...; Page Loading...; Page Loading...; Page Loading...; Page Loading...; Page Loading...; Page Loading...; Page Loading...; Page Loading...; Page Loading...; Page Loading...

(8 mentioned in)

Story Point Burn-up: (100.00%)

Feature Estimate: 1.0

Perentie Timing Synchronisation